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OPTi
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82C814 Docking Station Controller Preliminary Data Book
Revision: 2.0 912-2000-016 October 31, 1996
Copyright
Copyright (c) 1996, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to revise the design and associated documentation and to make changes from time to time in the content without obligation of OPTi Inc. to notify any person of such revisions or changes. Note: Before designing contact OPTi for latest Product Alerts, Applications Notes, and Errata for this product line.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 WWW: http://www.opti.com/
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Preliminary 82C814
Table of Contents
1.0 2.0 3.0 Features ............................................................................................................................ 1 Overview ........................................................................................................................... 1 Signal Definitions ............................................................................................................. 2
3.1 3.2 Terminology/Nomenclature Conventions ........................................................................................ 2 Signal Descriptions ............................................................................................................................ 6 3.2.1 3.2.2 3.2.3 3.2.4 3.3 Host Interface PCI Signals ..................................................................................................... 6 Docking Control and Sense Signals ....................................................................................... 7 PCI Docking Interface Pins..................................................................................................... 7 Interrupt Interface Pins ........................................................................................................... 8
Strap-Selected Interface Options ...................................................................................................... 9 3.2.5 Power, Ground and No Connect Pins .................................................................................... 9
3.4
Internal Resistors .............................................................................................................................10
4.0
Functional Description .................................................................................................. 11
4.1 4.2 4.3 4.4 4.5 4.6 OPTi Docking Station Controller Chipset.......................................................................................11 Chipset Compatibility.......................................................................................................................11 Interface Overview............................................................................................................................11 Device Type Detection Logic ...........................................................................................................12 Primary PCI Bus................................................................................................................................13 PCI-to-CardBus Bridge.....................................................................................................................13 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 Configuration Cycle ..............................................................................................................13 4.6.1.1 Translation Between Type 0 and Type 1 Configuration Cycles ............................13 Cycle from Host to Docking Interface ...................................................................................14 Master Cycle from Docking Interface ...................................................................................14 Inability to Complete a Posted Write ....................................................................................14 Cycle Termination by Target ................................................................................................14 4.6.5.1 Posted Write Termination .....................................................................................14 4.6.5.2 Non-Posted Write Termination..............................................................................14 4.6.5.3 Read (Prefetched or Non-Prefetched) Termination ..............................................14
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Preliminary 82C814
Table of Contents (cont.)
4.7 PCI Docking Station Operation .......................................................................................................15 4.7.1 4.7.2 4.7.3 4.7.4 4.8 Introduction...........................................................................................................................15 Procedure .............................................................................................................................15 Initial Setup...........................................................................................................................15 Action Upon Attachment of Dock..........................................................................................16
Status Change Service Routine ......................................................................................................17 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 Docking Event ......................................................................................................................17 Undocking Event ..................................................................................................................17 Notes on Undocking .............................................................................................................17 Retest ...................................................................................................................................17 PCI Clock Buffering ..............................................................................................................18
4.9
Interrupt Support ..............................................................................................................................18 4.9.1 4.9.2 PCI INTx# Implementation ...................................................................................................18 IRQ Driveback Logic.............................................................................................................18 4.9.2.1 Interrupt Status Return Latency ............................................................................19 4.9.2.2 End-of-Interrupt (EOI) ...........................................................................................20 4.9.2.3 EOI Handling.........................................................................................................20 Intel Serial IRQ Implementation............................................................................................21 4.9.3.1 Operation ..............................................................................................................21 Compaq Serial IRQ Implementation.....................................................................................22 4.9.4.1 Operation ..............................................................................................................22
4.9.3 4.9.4
5.0
82C814 Register Set ...................................................................................................... 23
5.1 5.2 5.3 Register State on Device Removal..................................................................................................23 Base Register Group ........................................................................................................................23 82C814-Specific Register Group .....................................................................................................31 5.3.1 5.3.2 5.3.3 5.3.4 5.4 IRQLATCH ...........................................................................................................................31 CLKRUN#.............................................................................................................................31 Slot Buffer Enable, Slew Rate, and Threshold Control.........................................................31 Dual ISA Buses ....................................................................................................................31
CardBus Register Group..................................................................................................................34 5.4.1 Power Control.......................................................................................................................34
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Table of Contents (cont.)
5.5 Docking Station Window Selection Group .....................................................................................37 5.5.1 5.5.2 Warning on Using Docking Station Windows .......................................................................37 Docking 5.5.2.1 5.5.2.2 5.5.2.3 Station Window Registers ......................................................................................37 Cycle Decoding .....................................................................................................38 Cycle Trapping ......................................................................................................38 ISA Window Selection...........................................................................................38
5.6
Register Summary ............................................................................................................................45
6.0
Electrical Ratings ........................................................................................................... 48
6.1 6.2 6.3 6.4 Absolute Maximum Ratings.............................................................................................................48 DC Characteristics: VCC = 3.3V or 5.0V 5%, TA = 0C to +70C.................................................48 AC Characteristics............................................................................................................................49 AC Timing Diagrams ........................................................................................................................50
7.0
Mechnical Package Outline........................................................................................... 51 IRQ Driveback Protocol ................................................................................. 53
Appendix A
A.1 A.2 A.3 A.4
Driveback Cycle Format ...................................................................................................................53 Edge vs Level Mode, IRQ Polarity ...................................................................................................54 Host Handling of IRQ Driveback Information.................................................................................54 External Implementation ..................................................................................................................55
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Preliminary 82C814
Table of Contents (cont.)
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List of Figures
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 6-1 Figure 6-2 Figure 6-3 Figure 7-1 Figure A-1 Figure A-2 Figure A-3 Multiple ISA Bus Support................................................................................................................. 1 Pin Diagram..................................................................................................................................... 3 Power-Up Timing ...........................................................................................................................10 82C814 Organization.....................................................................................................................11 Worst Case IRQ Driveback Latency Example ...............................................................................19 Setup Timing Waveform ................................................................................................................50 Hold Timing Waveform ..................................................................................................................50 Output Delay Timing Waveform.....................................................................................................50 144-Pin TQFP, Thin Quad Flat Pack.............................................................................................51 IRQ Driveback Cycle High-Priority Request ..................................................................................53 Dynamic Resourcing .....................................................................................................................55 Static Resourcing ..........................................................................................................................55
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Preliminary 82C814
List of Figures (cont.)
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List of Tables
Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table A-1 Table A-2 Signal Definitions Legend................................................................................................................ 2 Numerical Pin Cross-Reference List................................................................................................ 4 Alphabetical Pin Cross-Reference List ............................................................................................ 5 Strap Options for 82C814 Configurations........................................................................................ 9 Internal Keeper Resistor Scheme..................................................................................................10 Device Detection (CardBus Rules) ................................................................................................12 CLKRUN# Control Bits ..................................................................................................................13 Translation Feature Configuration Bit ............................................................................................13 Write Posting Associated Registers...............................................................................................14 Summary of Typical Settings (using IRQ5 for SMI) .......................................................................16 Register used to Delay Internal PCICLK to Compensate for Trace Delays...................................18 EOI Delay Setting ..........................................................................................................................20 Intel SIRQ Control Bit ....................................................................................................................21 Compaq SIRQ Control Bits............................................................................................................22 Base Register Group - PCICFG 00h-4Fh ......................................................................................23 Specific Register Group - PCICFG 50h-5Fh..................................................................................31 CardBus Register Set in System Memory .....................................................................................34 CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh .............................................34 Docking Station Access Windows .................................................................................................37 Power-on Reset, Card Removal Defaults for Docking Station Window Registers ........................37 Docking Station Window Registers - PCICFG 80h-FFh ................................................................38 82C814 Register Summary ...........................................................................................................45 Information Provided on a Driveback Cycle...................................................................................53 Information Provided on a Optional Data Phase 2 of IRQ Driveback Cycle ..................................54
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Preliminary 82C814
List of Tables (cont.)
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Preliminary 82C814
Docking Station Controller
Features
2.0
Overview
* Provides true hot docking and undocking * Supports 3.3V or 5.0V PCI dock * Host PCI bus can be 3.3V or 5.0V * Works in conjunction with 82C825 PCI-to-ISA bridge to provide reliable ISA support on the dock * Provides eight windows, selectable for memory or I/O * Offers additional fixed window for VGA * Supports INTA#, INTB#, INTC#, INTD# * Supports four bus masters * Generates PCI clocks for four devices * Bridge solution increases primary PCI bus bandwidth by off-loading transactions into buffers * Packaged in 144-pin TQFP (Thin Quad Flat Pack)
This document describes the OPTi 82C814 Docking Station Controller, a true bridge docking solution that allows software to treat the docking station like a dynamically insertable/ removable CardBus card. The PCI software interface conforms to the CardBus header layout, instead of the PCI-to-PCI bridge header layout, to overcome the limitations of PCI-to-PCI bridges. The docking controller implements a true PCI-PCI bridge with full buffering and synchronous or asynchronous operation.
Figure 2-1
Multiple ISA Bus Support
CPU
FireStar or Viper-N+ PCI Bus 0
Local ISA Bus
82C930 Sound Chip
(Ports 340-35Fh)
82C814 Docking Station Controller
92C178 PCI LCD/SVGA Controller PCI Bus 1
82C825 PCI-ISA Bridge
PCI Device
Docking ISA Bus
82C930 Sound Card
(Ports 340-35Fh)
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Preliminary 82C814
3.0 Signal Definitions
Table 3-1
Mnemonic CMOS The 82C814 chip provides a primary interface which is PCIbased. It also provides an independent attachment interface, which can be switched on and off dynamically.
Signal Definitions Legend
Description CMOS-level compatible Decoder External Ground Input Input/Output Internal Multiplexer Output Open drain (open-collector) CMOSlevel compatible Power Pull-down resistor Pull-up resistor Schmitt-trigger TTL-level compatible TTL-level compatible
3.1
Terminology/Nomenclature Conventions
Dcdr Ext G I I/O Int Mux O OD P PD PU S TTL
The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage level. The terms "assertion" and "negation" are used extensively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signals. The term "assert", or "assertion" indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term "negate", or "negation" indicates that a signal is inactive. The 82C814 has some pins that have multiple functions (denoted by "+" in the pin name). These functions are either: * cycle-multiplexed (always enabled and available when a particular cycle is in progress), * a strap option (configured at reset), * or selected via register programming. The tables in this section use several common abbreviations. Table 3-1 lists the mnemonics and their meanings.
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Figure 3-1 Pin Diagram
AD7 AD6 AD5 AD4 AD3 AD2 GND AD1 AD0 CLKRUN# IRQLATCH NC VENID+EXTCLK VCC ENVCC3 ENVCC5 CCD1# CVS1 CCLK0 GND CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CC/BE0# CAD8 CAD9 CAD10 GND CCLK1 C_VCC CAD11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
VCC C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 GND AD14 AD15 C/BE1# PAR SERR# PERR# LOCK# STOP# DEVSEL# VCC PCICLK GND TRDY# IRDY# FRAME# C/BE2# AD16 AD17 AD18 GND AD19 AD20 AD21 AD22 AD23 IDSEL VCC 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
82C814
C/BE3# AD24 AD25 AD26 AD27 AD28 AD29 GND AD30 AD31 REQ# GNT# VCC PCIRST# CCD2# CVS2 SOUT#+IRQSER SIN# PCIRQ3# PCIRQ2# GND PCIRQ1# PCIRQ0# CGNT3# CREQ3# CGNT2# CREQ2# CGNT1# CREQ1# CGNT0# CREQ0# CRST# CAD31 GND CCLK3 C_VCC
CAD12 CAD13 CAD14 CAD15 CC/BE1# CAD16 CPAR GND CSERR# CPERR# CBLOCK# CSTOP# CDEVSEL# CTRDY# CIRDY# GND CCLK2 C_VCC CFRAME# CC/BE2# CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 GND CC/BE3# CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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Preliminary 82C814
Table 3-2
Pin No. Pin Name
Numerical Pin Cross-Reference List
Pin Type I/O I/O I/O I/O I/O I/O G I/O I/O I/O I/O Pin No. Pin Name Pin Type I/O I/O I/O I/O O I/O I/O G I I O I I I O G O P O O I/O I/O I/O I/O I/O I/O I/O G O I/O I/O I/O I/O I/O I/O I/O P Pin No. Pin Name 74 CCLK3 75 GND 76 CAD31 77 CRST# 78 CREQ0# 79 CGNT0# 80 CREQ1# 81 CGNT1# 82 CREQ2# 83 CGNT2# 84 CREQ3# 85 CGNT3# 86 PCIRQ0# 87 PCIRQ1# 88 GND 89 PCIRQ2# 90 PCIRQ3# 91 SIN# 92 SOUT# IRQSER 93 CVS2 94 CCD2# 95 PCIRST# 96 VCC 97 GNT# 98 REQ# 99 AD31 100 AD30 101 GND 102 AD29 103 AD28 104 AD27 105 AD26 106 AD25 107 AD24 108 C/BE3# 109 VCC Pin Type O G I/O O I O I O I O I O I I G I I I O I/O I I I P I O I/O I/O G I/O I/O I/O I/O I/O I/O I P Pin No. Pin Name 110 IDSEL 111 AD23 112 AD22 113 AD21 114 AD20 115 AD19 116 GND 117 AD18 118 AD17 119 AD16 120 C/BE2# 121 FRAME# 122 IRDY# 123 TRDY# 124 GND 125 PCICLK 126 VCC 127 DEVSEL# 128 STOP# 129 LOCK# 130 PERR# 131 SERR# 132 PAR 133 C/BE1# 134 AD15 135 AD14 136 GND 137 AD13 138 AD12 139 AD11 140 AD10 141 AD9 142 AD8 143 C/BE0# 144 VCC Pin Type I I/O I/O I/O I/O I/O G I/O I/O I/O I I I O G I P O O I O O/OD I/O I I/O I/O G I/O I/O I/O I/O I/O I/O I P
1 AD7 2 AD6 3 AD5 4 AD4 5 AD3 6 AD2 7 GND 8 AD1 9 AD0 10 CLKRUN# 11 IRQLATCH 12 NC 13 VENID EXTCLK 14 VCC 15 ENVCC3 16 ENVCC5 17 CCD1# 18 CVS1 19 CCLK0 20 GND 21 CAD0 22 CAD1 23 CAD2 24 CAD3 25 CAD4 26 CAD5 27 CAD6 28 CAD7 29 CC/BE0# 30 CAD8 31 CAD9 32 CAD10 33 GND 34 CCLK1 35 C_VCC 36 CAD11
37 CAD12 38 CAD13 39 CAD14 40 CAD15 41 CC/BE1# 42 CAD16 43 CPAR 44 GND 45 CSERR# 46 CPERR# 47 CBLOCK# 48 CSTOP#
O I P O O I I O G I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O G O P I/O
49 CDEVSEL# 50 CTRDY# 51 CIRDY# 52 GND 53 CCLK2 54 C_VCC 55 CFRAME# 56 CC/BE2# 57 CAD17 58 CAD18 59 CAD19 60 CAD20 61 CAD21 62 CAD22 63 CAD23 64 GND 65 CC/BE3# 66 CAD24 67 CAD25 68 CAD26 69 CAD27 70 CAD28 71 CAD29 72 CAD30 73 C_VCC
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Preliminary 82C814
Table 3-3
Pin No. Pin Name
Alphabetical Pin Cross-Reference List
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin No. Pin Name Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O O O O O I Pin No. Pin Name 94 CCD2# 19 CCLK0 34 CCLK1 53 CCLK2 74 CCLK3 49 CDEVSEL# 55 CFRAME# 79 CGNT0# 81 CGNT1# 83 CGNT2# 85 CGNT3# 10 CLKRUN# 51 CIRDY# 43 CPAR 46 CPERR# 78 CREQ0# 80 CREQ1# 82 CREQ2# 84 CREQ3# 77 CRST# 45 CSERR# 48 CSTOP# 50 CTRDY# 35 C_VCC 54 C_VCC 73 C_VCC 18 CVS1 93 CVS2 127 DEVSEL# 15 ENVCC3 16 ENVCC5 121 FRAME# 7 GND 20 GND 33 GND 44 GND 52 GND Pin Type I O O O O I O O O O O I/O O I/O I I I I I O I I I P P P I I O O O I G G G G G Pin No. Pin Name 64 GND 75 GND 88 GND 101 GND 116 GND 124 GND 136 GND 97 GNT# 110 IDSEL 122 IRDY# 11 IRQLATCH 129 LOCK# 12 NC 132 PAR 125 PCICLK 86 PCIRQ0# 87 PCIRQ1# 89 PCIRQ2# 90 PCIRQ3# 95 PCIRST# 130 PERR# 98 REQ# 131 SERR# 91 SIN# 92 SOUT#+ IRQSER 128 STOP# 123 TRDY# 14 VCC 96 VCC 109 VCC 126 VCC 144 VCC 13 VENID+ EXTCLK I/O I I I I I I O O O/OD I I/O O O P P P P P I/O Pin Type G G G G G G G I I I I/O I
9 AD0 8 AD1 6 AD2 5 AD3 4 AD4 3 AD5 2 AD6 1 AD7 142 AD8 141 AD9 140 AD10 139 AD11 138 AD12 137 AD13 135 AD14 134 AD15 119 AD16 118 AD17 117 AD18 115 AD19 114 AD20 113 AD21 112 AD22 111 AD23 107 AD24 106 AD25 105 AD26 104 AD27 103 AD28 102 AD29 100 AD30 99 AD31 21 CAD0 22 CAD1 23 CAD2 24 CAD3 25 CAD4
26 CAD5 27 CAD6 28 CAD7 30 CAD8 31 CAD9 32 CAD10 36 CAD11 37 CAD12 38 CAD13 39 CAD14 40 CAD15 42 CAD16 57 CAD17 58 CAD18 59 CAD19 60 CAD20 61 CAD21 62 CAD22 63 CAD23 66 CAD24 67 CAD25 68 CAD26 69 CAD27 70 CAD28 71 CAD29 72 CAD30 76 CAD31 143 C/BE0# 133 C/BE1# 120 C/BE2# 108 C/BE3# 47 CBLOCK# 29 CC/BE0# 41 CC/BE1# 56 CC/BE2# 65 CC/BE3# 17 CCD1#
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Preliminary 82C814
3.2
3.2.1
Signal Descriptions
Host Interface PCI Signals
Pin No. 99, 100, 102:107, 111:115, 117:119, 134, 135, 137:142, 1:6, 8, 9 108, 120, 133, 143 132 Signal Type I/O Signal Description Address and Data Lines 31 through 0: This bus carries the address during the address phase and the data during the data phase of a PCI cycle. During the address phase these pins are inputs only and during the data phase they are I/Os.
Signal Name AD[31:0]
C/BE[3:0]#
I
Bus Command and Byte Enables 3 through 0: These inputs provide the command type information during the address phase and carry the byte enable information during the data phase. Parity: This bit carries parity information for both the address and data phases of PCI cycles. During the address or data write phase of a PCI cycle this pin is an input only. During the data read phase it acts as an output only. PCI Clock: Provides timing for all transactions on the host PCI bus; normally 33MHz. This same clock can be used for timing the slot interfaces, or can be divided. The slot interfaces can also run from the alternative EXTCLK input. Drive Vendor ID: This pin can be used to enable an external tristate buffer to drive vendor ID bits onto the PCI bus. This feature allows system card designers to drive a unique PCI card ID for identification by software. External Clock: Provides alternative clock source for transactions on the slot interface PCI bus. The frequency can be any value but is usually 20MHz or 25MHz. It should be tied low if not used. This pin is automatically sensed just after reset time to determine whether an external clock frequency is being applied. If not, the function defaults to VENID#. Clock Run: Pulled low by any device needing to use the PCI bus. If no devices pull this pin low, the host PCI bus controller is allowed to stop the PCICLK signal. The interrupt logic of the 82C814 uses this signal to request a restart of PCICLK in order to send an interrupt request. Interrupt Latch: For use on chipsets without IRQ driveback capability, the 82C814 logic can drive this line low to drive ISA IRQ lines using an external latch. This pin is also a strap option, refer to Section 5.3 Cycle Frame: Driven by PCI bus masters to indicate the beginning and duration of an access. Initiator Ready: Asserted by the PCI bus master to indicate that it is ready to complete the current data phase of the transaction. Target Ready: Asserted by the PCI bus target (when the 82C814 is a slave) to indicate that it is ready to complete the current data phase of the transaction. PCItype devices on the slot interfaces return CTRDY# to the 82C814, which in turn drives TRDY# to the host. The 82C814 logic drives TRDY# directly for 82C814 configuration register accesses. Stop: Used by the target to request that the master stop the current transaction and retry it later. The 82C814 logic uses this mechanism to back-off from a claimed cycle and generate an SMI through the IRQ driveback cycle, for example.
PAR
I/O
PCICLK
125
I
VENID#
13
O
EXTCLK
I
CLKRUN#
10
I/O
IRQLATCH
11
I/O
FRAME# IRDY# TRDY#
121 122 123
I I O
STOP#
128
O
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3.2.1 Host Interface PCI Signals (cont.)
Pin No. 129 Signal Type I Signal Description Lock: Indicates an atomic operation that may require multiple transactions to complete. The signal can be asserted to the 82C814 by any host bus PCI master, and is driven by the 82C814 logic in response to the current slot interface bus master driving its CBLOCK# signal. Device Select: Driven by the 82C814 logic when it decodes its address as the target of the current access via either positive or subtractive decoding. Parity Error: All devices use this signal to report data parity errors during any PCI transaction except a Special Cycle. System Error: The 82C814 logic uses this line to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. This pin has an open drain output. Bus Request: The 82C814 logic uses this signal to gain control of the PCI bus. The logic also uses this pin to generate an interrupt driveback request. Bus Grant: The system grants the bus to the 82C814 chip using this signal. ID Select: This signal is the "chip select" for the controller. This input simply connects to one of the upper address lines to select the controller for configuration cycles. Reset: Main chip reset input.
Signal Name LOCK#
DEVSEL# PERR# SERR#
127 130 131
O O O/OD
REQ# GNT# IDSEL
98 97 110
O I I
PCIRST#
95
I
3.2.2
Docking Control and Sense Signals
Pin No. 17 94 18 93 16 15 Signal Type I I I I O O 5.0V VCC Enable: Used to turn on power to 5.0V dock. 3.3V VCC Enable: Used to turn on power to 3.3V dock. Signal Description Connection Detect 1 and 2, Voltage Sense 1 and 2: CCD1-2# and CVS1-2 are used to determine proper dock attachment and to sense its voltage.
Signal Name CCD1# CCD2# CVS1 CVS2 ENVCC5 ENVCC3
3.2.3
PCI Docking Interface Pins
Pin No. 76, 72:66, 63:57, 42, 40:36, 32:30, 28:21 77 Signal Type I/O Signal Description Multiplexed Address and Data Lines 31 through 0: These pins are the multiplexed PCI address and data lines. During the address phase, these pins are outputs for PCI slave cycles and inputs for PCI master cycles. During the data phase, these pins are outputs during PCI write cycles and inputs during PCI reads. Reset: Used to reset the docking station PCI bus. This signal defaults to "asserted" until specifically programmed to go high.
Signal Name CAD[31:0]
CRST#
O
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3.2.3 PCI Docking Interface Pins (cont.)
Pin No. 65, 56, 41, 29 43 Signal Type O Signal Description Bus Command and Byte Enables 3 through 0: These pins are the multiplexed PCI command and byte enable lines. Normally outputs, these pins are inputs during master cycles. Parity: This signal is an input either during PCI slave cycles for address and write data phases or during PCI master cycle for read data phase; otherwise it is an output. Clock 3 through 0: These pins generate individual clocks to each PCI device on the dock. Cycle Frame: The 82C814 drives this signal to indicate the beginning and duration of an access. Initiator Ready: The 82C814 drives this signal to indicate its ability to complete the current data phase of the transaction. Target Ready: The 82C814 monitors this input from the slot interface slave device to determine when it can complete the cycle. PCI devices on the slots return CTRDY# to the 82C814 which in turn drives host TRDY#. Stop: This signal is used by the target to request the master to stop the current transaction. The 82C814 will back-off the current cycle and retry it later. Bus Lock: The 82C814 uses this signal to indicate an atomic operation that may require multiple transactions to complete. Device Select: This signal is normally an input from the slot interface device claiming the cycle. The 82C814 claims the cycle ahead of time on the host side. Parity Error: All slot interface devices use this signal to report data parity errors, during any PCI transaction except a Special Cycle. System Error: All slot interface devices use this signal to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Bus Master Request Lines 3 through 0: Request/grant signal pairs are provided to accommodate up to four PCI bus masters on the docking station. Bus Grant Lines 3 through 0: Request/grant signal pairs are provided to accommodate up to four PCI bus masters on the docking station.
Signal Name CC/BE[3:0]#
CPAR
I/O
CCLK[3:0] CFRAME# CIRDY# CTRDY#
74, 53, 34, 19 55 51 50
O O O I
CSTOP# CBLOCK# CDEVSEL# CPERR# CSERR#
48 47 49 46 45
I O I I I
CREQ[3:0]# CGNT[3:0]#
84, 82, 80, 78 85, 83, 81, 79
I O
3.2.4
Interrupt Interface Pins
Pin No. 86 87 89 90 Signal Type I I I I Signal Description PCI Interrupt 0: From docking station PCI Interrupt 1: From docking station PCI Interrupt 2: From docking station PCI Interrupt 3: From docking station
Signal Name PCIRQ0# PCIRQ1# PCIRQ2# PCIRQ3#
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3.2.4 Interrupt Interface Pins (cont.)
Pin No. 92 Signal Type O I/O 91 I Signal Description SeriaI Out: Intel Serial IRQs output for docking station devices using serial IRQs IRQ Serial: Compaq Serial IRQs for docking station devices using serial IRQs Serial In: Intel Serial IRQs input for docking station devices using serial IRQs
Signal Name SOUT# IRQSER SIN#
3.2.5
Power, Ground and No Connect Pins
Pin No. 7, 20, 33, 44, 52, 64,75, 88, 101, 116, 124, 136 14, 96, 109, 126, 144 35, 54, 73 12 Signal Type G Signal Description Ground Connection
Signal Name GND
VCC
P
Power Connection: For Host Interface
C_VCC NC
P
Power Connection: For Docking Interface No Connection: This pin should not be connected.
3.3
Strap-Selected Interface Options
ing actual use the resistors consume power only while programming voltage is selected to the cards, at which time the additional current draw would be 5.0V/10k ohm = 0.5mA. The strapping possibilities are listed in Table 3-4.
The 82C814 CardBus Controller can be strapped to operate in one of several different modes depending on its implementation in the system. Strap options are registered at chip reset time. The selection straps are normally 10k ohm resistors engaged full-time. Dur-
Table 3-4
Strap Options for 82C814 Configurations
Feature Core Voltage Select No Strap 3.3V Core and PCI host interface Pulled down by 10k ohm Resistor at Reset 5.0V Core and PCI host interface
Strap Selection IRQLATCH
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3.4 Internal Resistors
Figure 3-2 shows the functional timing relationships of software power-up and reset commands to the signals output by the power cycle state machine. The 82C814 slot interfaces are provided with pull-up and pulldown resistors internal to the chip. The resistors are active at the times indicated in Table 3-5. Table 3-5 refers to the chip state with no card inserted, a powered-down card inserted, or a docking station attached.
Table 3-5
Internal Keeper Resistor Scheme
Signal Group 82C814 Action with No Attachment Pull up to core VCC to detect dock insertion/removal Pull down 82C814 Action after Detecting Docking Station Pull up to core VCC Pull down until interface is powered up
Dock Detect: Address/Data:
CCD1-2# CAD[31:0] CC/BE[3:0]# CPAR CRST# CFRAME# CIRDY# CTRDY# CDEVSEL# CSTOP# CPERR# CBLOCK# CCLK[3:0] CREQ[3:0]# CSERR#
Reset: Frame: PCI Control/Status:
Driven low Pull down Pull down
Driven according to PCICFG 3Eh[6] None None
Clock: Request: Open Drain:
Pull down Pull up to card VCC Pull up to card VCC
Disable pull-down (clock input is always driven) None None
Figure 3-2
Power-Up Timing
Software writes CardBus 010h[5:4] = 11 (3.3V select) Pull-downs disabled VCC3 output signal CardBus 000h[3] = 1 (power cycle complete)
Pull-ups enabled, Output signals are driven Software sees power cycle complete, writes PCICFG 3Eh = 0 (deassert CRST#) CRST#
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4.0
4.1
Functional Description
OPTi Docking Station Controller Chipset
compliant system. DMA may require special software support on non-OPTi systems. Interrupts may require external TTL support.
The OPTi Docking Station solution is comprised of two devices. The minimum configuration requires one chip, the 82C814 part. * The 144-pin 82C814 Docking Controller handles the signal transfer for a complete PCI bus, including interrupts and clock generation. * The 82C825 PCI/ISA Bridge converts PCI signals back into ISA signals. No 82C825 device is required in the system, but one can be added as an option to support ISA peripherals in an attached docking station that connects through the PCI bus interface. The 82C825 is discussed in a separate document. The multiple interface arrangement offers the maximum in system design flexibility.
4.3
Interface Overview
The OPTi 82C814 Docking Station Controller Chipset uses two independent external interfaces. The terms host interface and docking interface are used throughout this document to describe these interfaces. * The host interface provides industry standard PCI signals to the host system. The interface also can be programmed to operate in a special (non PCI-standard) mode to allow driveback of interrupt requests from the docking interfaces. * The docking interface duplicates the primary PCI signal set. It is completely isolated from the primary PCI bus. The interface signal groups used to integrate the OPTi Docking Station Controller Chipset into the standard system are described in the following sections. Figure 4-1 illustrates the interaction of the components of the OPTi Docking Station Controller Chipset.
4.2
Chipset Compatibility
Because the OPTi Docking Station Controller Chipset is based on a PCI host interface, it can be used with any PCI-
Figure 4-1
82C814 Organization
PCI-to-CardBus Bridge #0
PCI Ctrl, Address, Data
PCI
H o s t P C I PCICLK
P r i m a r y P C I B u s
PCI Function #0 Cfg. Registers Master Req Bus Arbiter Logic IRQs
REQ# GNT#
S e c o n d a r y P C I B u s
IRQ Driveback Logic
D o c k i n g
PCI Slots
Clock Generation Logic
PCIRQ[3:0]#
S t a t i o n
82C825 PCI-to-ISA Bridge
ISA Slots
External Clock Source
CCLK[3:0]
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The logic implements several functional blocks that interact as indicated. The functional blocks shown in the diagram are briefly described below. * The 82C814 takes its control, address, and data information from its primary PCI bus, which is usually controlled by the host PCI interface but can also be controlled by a master on the docking interface. * The 82C814 logic implements a PCI-to-PCI (Card Bus) bridge controlled by PCI Configuration Registers. These configuration registers are accessed from the primary PCI bus. Any bus master, including a master on the docking interface, can program these registers. The PCI Configuration Registers consist of standard CardBus registers at indexes 00h-47h and OPTi 82C814 architecture-specific registers at indexes 48h-FFh. Settings in these registers control host interface operations, select architecture-specific settings such as interrupt routing to the host, and provide PCI status to the host on request. The register set is accessed as PCI Function 0 of the 82C814 device. * The PCI-to-PCI bridge serves to connect the primary PCI bus to an independent secondary PCI bus. It is this secondary bus that interfaces externally to a docking station. If no dock is attached, software can still access the configuration registers for the bridge. * The bus arbiter logic takes master requests for bus ownership for the purposes of: 1) Driving back IRQs; 2) Giving PCI master control to one of the secondary PCI buses. Driving back IRQ status always has highest priority. * Devices connected to the docking interface can transmit interrupts to the host system through the IRQ driveback logic. Docking station PCI devices can generate INTA#, INTB#, INTC#, and INTD# which the 82C814 logic converts to an interrupt. If the host system chipset does not provide the proper logic for recognition of this driveback cycle, IRQ information can be latched externally to generate discrete signals. * Clock generation logic is provided to use either the primary PCICLK input for synchronous operation, or an external clock input for asynchronous operation. Four separate output clocks are provided, and can be skew-compensated to adjust for varying board trace lengths. The logic subsystems of the 82C814 Docking Station Controller are described in detail in the following sections.
4.4
Device Type Detection Logic
The 82C814 logic includes attachment detection logic and a power control state machine to determine what type of dock has been attached to the docking interface. The power control state machine follows the algorithm provided by the CardBus specification, with a slight modification for docking station detection. Table 4-1 lists the device determination rules. Although the state machine follows the rules for CardBus device detection, only docking stations are considered valid attachments.
Table 4-1
CCD2# GND
Device Detection (CardBus Rules)
CCD1# Short to CVS1 GND GND GND Short to CVS2 GND Short to CVS1 Short to CVS2 GND GND GND GND GND GND CVS2 Open Short to CCD2# GND Short to CCD2# Short to CCD1# Open GND Short to CCD1# Open Open Open GND GND GND CVS1 Short to CCD1# GND Short to CCD2# Open Open Short to CCD2# Short to CCD1# GND Open GND GND Open GND GND Key LV LV LV LV LV LV --5.0V LV 5.0V LV LV 5.0V Card Type 3.3V CardBus 3.3/x.xV CardBus 3.3/x.x/y.yV CardBus x.xV CardBus x.x/y.yV CardBus y.yV CardBus 3.3V Docking Station 5.0V Docking Station 5.0V PCMCIA 3.3V PCMCIA 3.3/5.0V PCMCIA x.xV PCMCIA x.x/3.3V PCMCIA x.x/3.3/5.0V PCMCIA
Short to CVS2 Short to CVS1 Short to CVS2 GND Short to CVS1 GND GND GND GND GND GND GND GND
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4.5 Primary PCI Bus
4.6.1.1 Translation Between Type 0 and Type 1 Configuration Cycles The 82C814 logic converts Type 1 configuration cycles on the host PCI bus to Type 1, Type 0, or a Special Cycle as is typically required of a PCI-to-PCI bridge. However, in a PCIto-PCI bridge, Type 1 configuration cycles on the secondary PCI bus can be converted only to Type 1 or Special Cycles on the primary bus, never to Type 0. The 82C814 logic is different from the standard PCI-to-PCI bridge in this regard. The 82C814 allows the secondary to act as a primary. PCICFG 52h[0] is used to enable this feature. With this feature selected, master devices on the docking station interface can program the PCI configuration registers of the 82C814 (and any other PCI device on the host PCI bus). To do so, the secondary bus master must generate a Type 1 configuration cycle. The 82C814 logic will pass this to the primary as a Type 0 configuration cycle. Since the 82C814 PCI configuration registers sit on the primary, they are also accessible this way. Thus, on the primary the 82C814 acts as both initiator by generating the configuration cycle, and as target by claiming the cycle it just generated. Note that secondary bus masters can access PCI configuration registers on any primary bus device, not just the 82C814. The host interfaces to the 82C814 chip through the primary PCI bus. This bus operates according to PCI standards, including the later addition of the CLKRUN# signal. CLKRUN# is normally controlled by the host, but at certain times can be driven low by the 82C814 chip when the chip is requesting that PCICLK be restarted or sped up. Refer to the PCI Mobile Design Guide for the requirements of CLKRUN#. CLKRUN# is controlled by PCICFG 50h[2]. However, even if CLKRUN# is enabled, attaching a docking station will cause CLKRUN# to always request a running primary clock because docking station PCI device CLKRUN# support is not available.
4.6
PCI-to-CardBus Bridge
The PCI-to-CardBus bridge circuit of the 82C814 chip recognizes the cycle being performed by the current system bus master and responds as required.
4.6.1
Configuration Cycle
If the access is a configuration cycle, the PCI bridge simply accesses the local PCI Configuration Register set directly. The PCI cycle controller claims all configuration accesses to PCI Function 0 of the 82C814 chip.
Table 4-2
7 PCICFG 50h
CLKRUN# Control Bits
6 5 4 3 2 1 0 Default = 01h CLKRUN# on host interface): 0 = Enabled per PCI 1 = Disabled, CLKRUN# tristated
PCI Host Feature Control Register
Table 4-3
7 PCICFG 52h
Translation Feature Configuration Bit
6 5 4 3 2 1 0 Default = 0Fh Type 1 to Type 0 conversion blocked from secondary to primary: 0 = No 1 = Yes (Default)
Docking Feature Control Register 2
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4.6.2 Cycle from Host to Docking Interface 4.6.5 Cycle Termination by Target
For a cycle from the host to a docking interface with a docking station attached, the PCI bridge resynchronizes the cycle and passes it to the external PCI device. Docking PCI devices can run either synchronously at 33MHz, or asynchronously at 16MHz, 20MHz, or 25MHz. The bridge claims the cycle if it falls into one of the ranges programmed in the Window Registers of the PCI Configuration Register set. The PCI-to-CardBus bridge logic responds to cycle termination by target devices in various ways for each transaction type being terminated. 4.6.5.1 Posted Write Termination Retry or Disconnect - The 82C814 logic retries the write cycle at least 256 times, and may continue trying indefinitely, according to the setting of PCICFG 5Eh[2:0]. When the logic reaches the retry limit, it generates SERR# on the master interface. No target abort will be signalled in the PCI Status Register, but software can read 82C814-Specific Register 5Fh to determine whether the retry limit was exceeded. Target Abort or No Response - The logic generates SERR#+CSERR# on the master interface. Software reads the PCI Status Register to determine that a target abort occurred. 4.6.5.2 Non-Posted Write Termination Retry, Disconnect, or Target Abort - The logic simply conveys the target response to the initiator. No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic terminates the cycle to the initiator normally. If bit 3Eh[5] = 1, the logic generates target abort to the initiator. 4.6.5.3 Read (Prefetched or Non-Prefetched) Termination Retry, Disconnect, or Target Abort - The logic simply conveys the target response to the initiator. No Response - If PCICFG 3Eh[5] = 0, the 82C814 logic terminates the cycle to the initiator normally and returns FFFFFFFFh as the data read. If bit 3Eh[5] = 1, the logic generates target abort to the initiator.
4.6.3
Master Cycle from Docking Interface
For a master cycle from the docking interface, the 82C814 logic presents the cycle on the host PCI bus as master. If the cycle is directed to a device on the other docking interface, the 82C814 logic claims the cycle immediately, as a slave, since the address ranges are already programmed into the Base Address Registers for that docking station. If the cycle is not claimed by the other docking station and no host device claims it, the 82C814 generates a master abort.
4.6.4
Inability to Complete a Posted Write
The 82C814 logic provides write posting in both the downstream and upstream PCI directions. There is a special situation that arises when the target of posted write data is unable to complete the transaction. Normally, a target retry or a disconnect will result in the 82C814 logic retrying the access until it has completed the transfer of posted data. However, after the programmed number of retries has been attempted, the logic must report the error condition back to the host. The 82C814 provides only one mechanism to return the error: the SERR# pin. The host must then decide how to handle the SERR# generation, either by generation of an NMI or some other means. The 82C814 PCI configuration register set provides a register to program the number of retries before the logic gives up and generates SERR#, as shown in Table 4-4.
Table 4-4
7 PCICFG 5Eh
Write Posting Associated Registers
6 5 4 3 2 1 0 Default = 07h Retry Limit: These bits relate to the number of times that the 82C814, as a slave, will retry accesses on the primary. If this limit is exceeded, the 82C814 generates SERR# to the host. 000=28 001=2 011=2
10
Primary Retry Limit Register
100=216 101=220 110=224 111= Infinite retries (Default)
010=212
14
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Table 4-4
7 PCICFG 5Fh -
Write Posting Associated Registers (cont.)
6 5 4 3 2 1 0 Default = 00h
82C814 Retry Count Readback Register (RO)
This register returns the number of retry attempts made. More than 256 retries are indicated by FFh. Used for diagnostic purposes. Read-only. Separate counts are maintained for primary and secondary. Bit 5Eh[3] selects the count being read back. Bridge Control Register - Byte 0 Response to master abort on slot interface: 0 = Ignore 1 = Signal with target abort or SERR# Default = 40h
PCICFG 3Eh
4.7
PCI Docking Station Operation
4.7.2 Procedure
The docking concept follows the Yenta specification. However, a more flexible set of registers is available for docking that allows eight windows instead of the four offered by Yenta. Either the Yenta window registers (PCICFG 1C-3Bh) or the docking registers (PCICFG 80-FFh) can be used. The docking window registers also allow finer control over window sizes than do the Yenta window registers.
OPTi docking is based on the CardBus concept: the docking station can be treated like a CardBus card being plugged into or removed from the system at any time. The docking interface is fully isolated and allows the host system to recover in case of problems on the dock. Secondary bus PCI docking solutions are not yet supported by Windows '95. Consequently, current system designs must include software written specifically for the 82C814 chip. The rest of this section describes the basics of the support software needed.
4.7.3
Initial Setup
4.7.1
Introduction
The following programming should be performed at system initialization time, and does not need to be repeated after. * Enable Host Chipset Bus Preemption. Write SYSCFG 1Eh[3] = 1 on the Viper-N+ and FireStar chipsets. * Establish Status Change Interrupt. Write PCICFG 4Ch with the IRQ that should be generated when the dock is attached or removed. Any available IRQ can be used. On FireStar, selecting IRQ2 will generate an SMI and IRQ13 will generate an NMI. These selections are not available on Viper-N+. However, normal IRQs can be programmed on the Viper-N+ chipset to generate an SMI or NMI if desired, through the following approach: 1. Use SYSCFG 64h and A4h to select the IRQ to use for SMI generation. 2. Write SYSCFG 57h[6] = 1 to enable INTRGRP to generate PMI#6 when the selected IRQ goes active. 3. Write SYSCFG 59h[5:4] = 11 to enable PMI#6 to generate SMI.
The 82C814 register set follows the Yenta standard; the registers are virtually the same whether in CardBus mode or in Docking mode. However, there are two differences from a programming point of view. * A CardBus card can be identified as PCICFG 68h[5:4] = 10. A Docking Station is identified by PCICFG 68h[5:4] = 11. * A CardBus card has only one interrupt, mapped to PCIRQ0#. A Docking Station has four interrupt pins, mapped through PCIRQ[3:0]#. When a docking station is attached to the interface, the power control state machine of the 82C814 recognizes the docking station. A docking station is the only valid attachment to the 82C814 chip.
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* Establish IRQ Driveback Address. Write PCICFG 5457h with an I/O address to use for IRQ driveback. The default value is 33333330h, but any unused value is fine. Ideally the address should be greater than FFFFh to prevent conflicts with ISA I/O address space. Write the same value to the IRQ Driveback registers in the host chipset (Viper-N+ or FireStar). The registers are at the same PCI offset, but different PCI device: PCIDV1 5457h. * Select PCI Bus Number of Docking Station. PCICFG 19h selects the PCI bus number on the secondary side of the bridge. A value of 01h is typical. * Select Total Number of Downstream Buses. PCICFG 1Ah selects the number of the last downstream PCI bus. A value of 01h is typical, but if the docking station also uses an 82C824 chip, this value should be 02h. * Program the Time-out Value. PCICFG 1Bh should be set to FFh. * Program the Latency Timer. PCICFG 0Dh should be set to FFh. * Select the Status Change Events. PCICFG 64h[3:0] select the events that will cause a status change interrupt in the future. Typically writing PCICFG 64h = 06h is adequate. Also write PCICFG 60h = 0Fh to clear any pending events. Table 4-5 summarizes the typical settings for system initialization.
4.7.4
Action Upon Attachment of Dock
At idle, with no device attached, the CD1-2# pins are pulled high internal to the 82C814 chip. CVS1-2 are driven low. All other interface lines are pulled low at this time; the docking interface itself can remain unpowered. The 82C814 monitors the CD1-2 lines to determine a docking event. When a docking station is attached, the 82C814 sees CD1# and CD2# go low, because the docking station connector has these lines hard-wired as follows: * CD1# is connected to CVS1 for a 3.3V docking station, or to CVS2 for a 5.0V docking station. * CD2# is connected to ground. The 82C814 card detection sequencer waits for the time set in PCICFG 50h[3], then performs a test on these lines to determine the type of device attached. Once the test is complete, the 82C814 generates an interrupt to the IRQ configured in PCICFG 4Ch.
Table 4-5
Register
Summary of Typical Settings (using IRQ5 for SMI)
Byte 3 Byte 2 Byte 1 Byte 0
82C814 Register PCICFG 4Ch PCICFG 54h PCICFG 0Ch PCICFG 18h PCICFG 64h PCICFG 60h -33h -FFh ---33h -01h ---33h FFh 01h --15h (IRQ5) 30h -00h 06h 0Fh
Viper N+ Register (assuming IRQ5) PCIDV1 54h SYSCFG 64h SYSCFG 57h SYSCFG 59h SYSCFG 1Eh 33h ----33h ----33h ----30h ****1***b(IRQ5) 01**0000b **11****b ****1***b
* These bits should be read first, then written to the same value.
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4.8 Status Change Service Routine
4. Select PCICLK skew through PCICFG 52h[7:4]. This value will have to be determined according to the design of the docking station. Depending on the type of PCICLK routing used on the docking station, the internal clock may need to be skewed 1-15ns. 5. Write PCICFG 3Eh[6] = 0 to deassert PCIRST# to the dock. The Docking Station devices can now be configured in the usual manner for PCI devices. Interrupt or SMI service software should perform the following steps: 1. Read PCICFG 68h[7, 5:4] to determine whether a docking station has been recognized. Test: PCICFG 68h[7] = 0? Yes - Device recognized. No - Device not recognized. Go to "Retest" section. Test: PCICFG 68[5:4] = 11? Yes - Docking station recognized. No - Not a docking station. Exit procedure so that CardBus software can handle event. 2. Read PCICFG 68h[2:1]. The card detection sequencer drives CVS1 and CVS2 low after detection, so CD1-2# will stay low. Test: PCICFG 68h[2:1] = 00? Yes - Docking confirmed. No - A non zero value indicates that the connection is not valid or that an undock event has taken place. 3. Read PCICFG 60h to determine the event that caused the interrupt. Write this same value back to the register to clear these events, and cause the IRQ line that was active to go inactive. Also clear PMI event on host chipset if this was an SMI. 4. Test: Was docking confirmed in step 2? Yes - Go to "Docking Event" section. No - Force a retest by writing PCICFG 6Dh[6] = 1, and go to step 1. If this is the second time through, then proceed to "Undocking Event" section.
4.8.2
Undocking Event
The following step should be followed if an undock event has been detected. 1. Test whether PCICFG 69h[0] = 1. If so, data may have been lost in the undocking event. On an undock event, no other steps are necessary. The controller automatically powers down the dock, tristates the interface, and asserts the CRST# line.
4.8.3
Notes on Undocking
When undocking, the user can notify the system software (Windows 95) first so that the system software can turn off the 82C814 docking side to make a graceful undock. This is the safest scheme to implement but is not always practical in a real system because of cost. If hot undocking is required without notifying the system software, shorter CD1-2# pins are required on the docking connector. The CD1-2# pins will change first. The 82C814 will complete the current cycle on the secondary, and will not attempt to start another. The undocking event generates an interrupt to the system, so that software can check to determine if any posted write data was left in the FIFO. PCICFG 5Fh returns the number of retries attempted in flushing the FIFO, which can be used to determine whether any data was left after the hot undock.
4.8.1
Docking Event
1. Read PCICFG 69h to determine the docking station voltage. 2. Power up the interface by writing PCICFG 70h[6:4] with the correct VCC value. PCICFG 70h is typically written to 20h for a 5.0V docking station. 3. Read PCICFG 68h again to check power cycling. Test: PCICFG 68h[3] = 1? Yes - Continue to next step. No - There is a problem. Check PCICFG 69h[1] to see if the VCC value chosen is allowable. If necessary, force a retest and then start over at step 1.
4.8.4
Retest
Whenever the result of a test is ambiguous, software should force the controller to retest the detection pins. Force a retest by writing PCICFG 6Dh[6] = 1, then start the full service routine over again. If after several times through this retest sequence the status cannot be determined, assume an "undocked" state.
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4.8.5 PCI Clock Buffering
erally required. Table 4-6 highlights the register used for compensating trace delays. The 82C814 logic provides register settings PCICFG 52h[7:4] to compensate for trace delays. Some compensation is gen-
Table 4-6
7 PCICFG 52h
Register used to Delay Internal PCICLK to Compensate for Trace Delays
6 5 4 3 2 1 0 Default = 0Fh
Docking Feature Control Register 2 Secondary PCICLK Skew:
This value selects the approximate delay, in nanoseconds, that the internal secondary PCICLK must be skewed in order to compensate for external buffer delays. 0000 = No delay ..... 1101 = 13ns 0001 = 1ns 1110 = 14ns 0010 = 2ns 1111 = 15ns
4.9
Interrupt Support
4.9.1 PCI INTx# Implementation
The PCI INTA#, INTB#, INTC#, and INTD# lines can be mapped to any of the primary side PCIRQ[3:0]# lines. PCICFG 48-4Ch provide controls for this mapping.
The 82C814 supports a total of four interrupt schemes from the secondary PCI bus. 1. PCI interrupts INTA#, INTB#, INTC#, and INTD# can be mapped internally to system PCIRQ[3:0]# lines. 2. PCI IRQ driveback cycles can generate any ISA interrupt. The 82C825 chip uses this scheme to generate interrupts in a parallel format back to the host controller via the 82C814 chip. 3. The Intel Serial IRQ scheme uses two wires, SIN# and SOUT#, along with the PCICLK to transmit interrupts in a serial format. 4. The Compaq Serial IRQ scheme uses a single wire, IRQSER, along with the PCICLK to transmit interrupts in a serial format. No matter how the interrupt arrives from the secondary, it is conveyed to the host chipset on the primary side through the IRQ driveback scheme. The available schemes are described below.
4.9.2
IRQ Driveback Logic
A detailed overview of the IRQ driveback cycle is provided in Appendix A. The logic used to implement this mechanism is relatively simple. The trigger events for a driveback cycle are any transition on an interrupt line, or an SMI event as enabled by the 82C814 configuration registers. The request goes to the Request Arbiter logic, which always gives the driveback cycle top priority. Once the REQ# pin is available, the Request Arbiter asserts REQ# on behalf of the IRQ Driveback logic and toggles REQ# according to the driveback protocol discussed in Appendix A. Once the host PCI controller returns GNT#, the driveback logic writes to the IRQ driveback address location specified in the PCI configuration registers as shown in Appendix A.
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4.9.2.1 Interrupt Status Return Latency An IRQ driveback cycle has predictable latency. Since the host is required to service a driveback cycle with the highest priority, interrupt latency depends solely on the time required for the current bus master to give up the bus after the host has removed its GNT# signal. Therefore, masters on the system must honor a latency timer time-out after their GNT# signal has been removed. With this requirement, maximum interrupt service latency can be predicted very accurately. A more important aspect of driveback latency is the ability of the host to inhibit activity that would be affected by IRQ status change delays. Figure 4-2 illustrates the problem. For each stage of IRQ status generation or resynchronization there is a penalty. In the case shown, the nominal latency is less than 400ns. However, even this low latency could result in false interrupt generation, as explained next.
Figure 4-2
Worst Case IRQ Driveback Latency Example
PCI-to-PCI Bridge #1
PCI Ctrl, Address, Data
H o s t P C I
P r i m a r y P C I B u s
REQ# GNT#
PCI
PCI Function #0 Cfg. Registers
Master Req
IRQs
D o c k i n g I n t e r f a c e
D o c k i n g S t a t i o n P C I
PCI Device
INTA#
Floppy Drive
IRQ6
82C825 PCI-to-ISA Bridge
REQ# GNT# INTB# IRQ14
IRQ4
Modem
Bus Arbiter Logic
IRQ Driveback Logic
PCI Device
Hard Disk
Driveback REQ# EOI Inhibition Latency: 1 PCICLK 30ns @ 33MHz
Driveback REQ# Resynchronization Latency: 1 PCICLK 60ns @ 16MHz
Driveback REQ# Recognition Latency: 3 PCICLKs 180ns @ 16MHz
Driveback REQ# Generation from IRQ Latency: 1 PCICLK 60ns @ 16MHz
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4.9.2.2 End-of-Interrupt (EOI) The primary concern for driveback delays is End of Interrupt (EOI) recognition at the 8259-compatible interrupt controller on the host system. At the end of interrupt service, software writes to the interrupting device (possibly across the 82C814 bridge) to command it to deassert its interrupt line. The software then generates an EOI command to the local 8259 interrupt controller, enabling it to generate another interrupt. However, there is a delay involved in passing the changed IRQ status from the interrupting device across the PCI bridge and generating the IRQ driveback cycle to the 8259 interrupt controller. Therefore, the 8259 interrupt controller could conceivably receive the EOI command while the incoming interrupt line still appears active. If the channel is programmed for level mode, the result would be a false interrupt. 4.9.2.3 EOI Handling The host handles this situation as follows if it has direct control of the interrupt controller, which is the case with OPTi PCI hosts. Whenever the host sees its REQ# input active, it inhibits EOIs until it recognizes whether the cycle is a driveback request. The host will be able to recognize a driveback request within three PCI clocks: a driveback request requires REQ# to go low for one clock, high for the next clock, and low again on the third clock. This process introduces a delay of 90ns at 33MHz and 180ns at 16MHz. The host can reenable EOI recognition at this time if the request is not for an IRQ driveback. However, a device across the PCI bridge, such as the docking station device on a secondary PCI bus, also uses the same driveback mechanism as the 82C814 does on the host side to generate an IRQ. Since the 82C814 logic has to wait three PCI clocks on the secondary bus before it recognizes a driveback cycle, it cannot assert REQ# to the host until it knows whether to generate a driveback request or a simple master request. This three clock penalty could result in an additional delay as high as 180ns if a 16MHz bus is being used. Therefore, the host device must have a programmable delay that it generates any time an EOI command is written to its 8259 interrupt controller. During this delay, IRQ writeback request activity signalled on the incoming REQ# lines must be serviced immediately, or in any case before the EOI is allowed to pass. The format of this register in OPTi chipsets is similar to that shown in Table 4-7. The system architecture determines the value that must be written to this register.
Table 4-7
7 PCIDV1 5Eh
EOI Delay Setting
6 5 4 3 2 1 0 Default = 00h Reserved Reserved Reserved
IRQ Scheme Management Register Reserved Reserved Reserved
End-of-Interrupt Holdoff bits [1:0]: The value of these bits selects the number of retries that will be forced on the PCI bus every time an attempt is made to write I/O Port 020h or 0A0h, where OCW2 of the interrupt controller is set. Multiple retries ensure that a device trying to generate an IRQ driveback will succeed before an EOI command takes effect. This feature eliminates the possibility that an EOI could be registered before a change in IRQ status gets back to the central interrupt controller.
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4.9.3 Intel Serial IRQ Implementation
The 82C814 chip supports the Intel standard of Serial IRQs. This two wire approach is very similar to the one-wire Compaq approach, but permits interrupt sharing between two devices on the line without any possible contention between devices. Only one control bit is required for the Intel serial IRQ scheme: PCICFG 4Fh[0] (as shown in Table 4-8). 4.9.3.1 Operation The Intel Serial IRQ protocol requires two pins, the SIN# input and the SOUT# output. Once PCICFG 4Fh[0] is set to 1, IRQ15 automatically becomes SIN# and IRQSER becomes SOUT#. In addition to these pins, the CLKRUN# protocol must be enabled to use Intel Serial IRQs. The sole function of SOUT# is to initiate a serial interrupt protocol sequence by generating a single low pulse; the logic will never introduce other IRQs into the frame at the starting end. After the SOUT# pulse has been sent out, the Intel Serial IRQ (ISIRQ) logic will keep sampling the SIN# pin. Once the SIN# data pin is sampled low, the ISIRQ logic enters Start state. The logic passes through all the SMI and IRQ states to sample the SIN# data pin for the corresponding SMI and IRQ values. All the sampled SMI and IRQ values are passed to the 8259 at the same time that they are sampled, without any delay. When all the SMI and IRQ states have been seen, the ISIRQ logic enters the Stop state. Once in Stop state, the ISIRQ logic will decide whether to initiate another serial interrupt sequence or not by monitoring the PMU stop PCI clock request (CLKRUN#). If such a PMU request is pending, then the ISIRQ logic will stay in the Stop state until the PMU request is removed. If there is no PMU stop PCI clock request, the ISIRQ logic will initiate another serial interrupt sequence and mask the PMU stop PCI request until it has finished one complete serial interrupt sequence.
Table 4-8
7 PCICFG 4Fh
Intel SIRQ Control Bit
6 5 4 3 2 1 0 Default = 00h Intel SIRQ (Intel Serial IRQ scheme): 0 = Disable 1 = Enable
Serial IRQ Control Register 2
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4.9.4 Compaq Serial IRQ Implementation
The 82C814 chip supports the Compaq standard of Serial IRQs. This one wire approach is very compact compared to the Intel two-wire approach, but if two devices on the line want to share the same interrupt, there may be brief contention since both devices drive the line low on one clock and high on the clock that immediately follows. Because of this contention, OPTi cannot guarantee against chip hardware failure if interrupts are shared in this mode. The Compaq Serial IRQ scheme requires the register bits. shown in Table 4-9.
Table 4-9
7 PCICFG 4Eh Compaq SIRQ HALT mode request: 0 = Active 1 = Halt
Compaq SIRQ Control Bits
6 5 4 3 2 1 0 Default = 00h Compaq SIRQ (Compaq Serial IRQ scheme): 0 = Disable 1 = Enable
Serial IRQ Control Register 1 Compaq SIRQ QUIET mode request: 0 = Continuous 1 = Quiet Compaq SIRQ data frame slots. Change only when the Serial IRQ logic is disabled or in Halt state. 0 = 17 slots 1 = 21 slots Compaq SIRQ Start frame width in PCI clocks. Change this setting only when Serial IRQ is disabled or in Halt state. 00 = 4 PCI clocks 01 = 6 PCI clocks 10 = 8 PCI clocks 11 = Reserved
PCICFG 4Fh Compaq SIRQ in HALT state (RO)? 0 = No 1 = Yes Compaq SIRQ in QUIET state (RO)? 0 = No 1 = Yes
Serial IRQ Control Register 2
Default = 00h
QUIET - PCICFG 4Eh[6] requests the next Serial IRQ cycle to be Continuous or Quiet mode. In mobile applications, use Continuous mode only. This is to guarantee that the host gains control of the Serial IRQ for suspend and APM stop clock. In application where the PCI clock never stops, use either mode. PCICFG 4Fh[6] can be read to determine the current state of the logic. HALT - PCICFG 4Eh[7] requests a temporary halt of the Serial IRQ controller as soon as the current cycle has returned to Idle state. Once in Halt state, the Serial IRQ configuration can be changed. After the logic has been put in Halt state, upon clearing this bit the logic will return to Continuous mode. PCICFG 4Fh[7] can be read to determine the current state of the logic. 4.9.4.1 Operation The Compaq Serial IRQ protocol requires one additional PCI sustained Tri-State pin, the IRQSER signal. For detailed Serial IRQ operation, refer to the "Serialized IRQ for PCI Systems" specification. After setting PCICFG 4Eh[0] = 1 to enable Compaq Serial IRQ (CSIRQ) mode, the CSIRQ controller initiates a Continuous mode Start frame. During the Data frame, the CSIRQ logic samples the IRQSER input for the corresponding SMI, IOCHCK#, and IRQ values, and then passes the sampled values to 8259.
At the end of the Data frame, the CSIRQ controller will sample the QUIET and HALT bits to determine whether the next Compaq Serial IRQ cycle will be Continuous mode, Quiet mode, or a temporary Halt state. * If the next cycle is sampled to be Continuous mode, IRQSER is asserted for three PCI clocks. Once the logic enters Idle state, it checks whether the PMU stop PCI clock request is pending. If so, the CSIRQ logic will stay in the Idle state until the PMU request is removed. * If the next cycle is sampled to be Quiet mode, IRQSER is asserted for two PCI clocks. Once the logic enters Idle state, it samples the IRQSER input to begin the Quiet mode cycle. Since the 82C814 has no control of the Start frame, this mode is not recommended for mobile application. * If the HALT bit is sampled active, then the CSIRQ logic asserts IRQSER for three PCI clocks to tell all the Serial IRQ devices that next cycle will be Continuous mode; the logic then enters Halt state. In Halt state, CSIRQ configuration can be changed. Clearing the HALT bit will immediately cause a Continuous mode Start frame to be generated. Once enabled, the Compaq Serial IRQ logic operates all the time when docked; no clock stop synchronization is needed.
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5.0 82C814 Register Set
disconnected from the interface (CCD1# and CCD2# both high). However, the 82C814-specific registers at PCICFG 48h-5Fh control global configuration and remain set to their programmed values even after a device is removed. The 82C814 Docking Controller chip provides a single group of programming registers, PCI-to-CardBus Bridge 0 Register Group, accessed through a PCI Configuration Cycle to Function 0 of the chip. Consists of CardBus Controller Base Register Group at PCICFG 00h-4Fh, 82C814-specific registers at 50h-5Fh, CardBus Control and Status Register Group at 60h7Fh, and Docking Station Window Register Group at 80hFFh. Note that the CardBus Control and Status Register Group can also be accessed in system memory space. This register group is defined in the following subsections.
5.2
Base Register Group
The registers below represent the standard group required for PCI peripheral device identification and configuration for a PCI-to-CardBus bridge. Note: In the tables that follow, all bits are R/W and their default value is zero, unless otherwise specified. R/W = Read/Write, RO = Read-only, and WO = Write-only
5.1
Register State on Device Removal
As a general rule, all PCI configuration registers default to their power-on reset value when the card or docking station is
Table 5-1
7 PCICFG 00h PCICFG 01h PCICFG 02h PCICFG 03h PCICFG 04h Address/data stepping: 0 = Disable (always) PCICFG 05h
Base Register Group - PCICFG 00h-4Fh
6 5 4 3 2 1 0 Default = 45h Default = 10h Default = 14h Default = C8h Default = 04h Bus master by docking interfaces: 1 = Enable (always) Respond to PCI mem accesses: 0 = No 1 = Yes Respond to PCI I/O accesses: 0 = No 1 = Yes Default = 00h Fast back-toback (RO): 0 = Disable (always) SERR# generation: 0 = Disable 1 = Enable Default = 00h
Vendor Identification Register (RO) - Byte 0 Vendor Identification Register (RO) Byte 1 Device ID (RO) - Byte 0 Device ID (RO) - Byte 1 PCI Command Register - Byte 0 PERR# generation: 0 = Disable 1 = Enable VGA palette snoop: 0 = Disable 1 = Enable Mem write and Invalidate (RO): 0 = Disable (always) Special Cycle (RO): 0 = Disable (always)
PCI Command Register - Byte 1 Reserved: Write bits as read.
PCICFG 06h Fast back-toback capability (RO): 0 = No (always) PCICFG 07h Parity error: 0 = No 1 = Yes Write 1 to clear System error: 0 = No 1 = Yes Write 1 to clear Received master abort: 0 = No 1 = Yes Write 1 to clear
PCI Status Register - Byte 0 Reserved (RO)
PCI Status Register - Byte 1 Received target abort: 0 = No 1 = Yes Write 1 to clear Signalled target abort: 0 = No 1 = Yes Write 1 to clear DEVSEL# timing (RO): 00 = Fast 01 = Medium (always) 10 = Slow 11 = Reserved
Default = 02h PERR# active as master: 0 = No 1 = Yes Write 1 to clear
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Table 5-1
7 PCICFG 08h PCICFG 09h PCICFG 0Ah
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 00h Default = 00h Default = 07h
Revision Register (RO) Programming Interface Class Code Register (RO) Class Code Register (RO) - Byte 0 Subclass Code bits: = 07h (PCI-to-Cardbus Bridge)
PCICFG 0Bh
Class Code Register (RO) - Byte 1 Base Class Code bits: = 06h (Bus Bridge)
Default = 06h
PCICFG 0Ch
Cache Line Size Register Not implemented
Default = 00h
PCICFG 0Dh
Latency Timer Register Indicates the time-out value for the primary PCI interface.
Default = 00h
PCICFG 0Eh Multi-function device (RO): 0 = No (always) PCICFG 0Fh
Header Type Register Layout type for 10-3Fh bytes bits [6:0] = 02h (PCI-to-CardBus Header Layout)
Default = 02h
BIST Register Not implemented
Default = 00h
PCICFG 10h -
CardBus Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
CardBus Socket Status and Control Base Address Bits: The 32-bit Cardbus Base Address Register selects the starting address in memory space of the CardBus socket status and control registers. Actual register addresses are calculated by adding the MEMOFST of the register to this base address. Bits [11:0] are read-only and are always 0, to indicate that the registers occupy 4KB of non prefetchable system memory space and starts on a 4KB boundary. CardBus Base Address Register - Byte 1: Address Bits [15:8] CardBus Base Address Register - Byte 2: Address Bits [23:16] CardBus Base Address Register - Byte 3: Address Bits [31:24] Reserved PCI Secondary Bus Status Register - Byte 0 Reserved (RO) Default = 00h Default = 00h Default = 00h Default = 00h Default = 00h
PCICFG 11h PCICFG 12h PCICFG 13h PCICFG 14h-15h PCICFG 16h Fast back-toback capability on docking interface PCI bus (RO): 0 = No (always)
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Table 5-1
7 PCICFG 17h Parity error on docking interface PCI bus: 0 = No 1 = Yes Write 1 to clear PCICFG 18h Received system error on docking interface PCI bus: 0 = No 1 = Yes Write 1 to clear
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 02h PERR# active as master on docking interface PCI bus (RO): 0 = No 1 = Yes Default = 00h
PCI Secondary Bus Status Register - Byte 1 Received master abort on docking interface PCI bus (RO): 0 = No 1 = Yes Received target abort on docking interface PCI bus (RO): 0 = No 1 = Yes Signalled target abort on docking interface PCI bus: 0 = No 1 = Yes Write 1 to clear DEVSEL# timing on docking interface PCI bus (RO): 00 = Fast 01 =Medium (always) 10 = Slow 11 = Reserved
Primary PCI Bus Number Register
Indicates the number of the PCI bus to which the host interface of the 82C814 chip is connected. Defaults to 0. The logic uses this value to determine whether Type 1 configuration transactions on the docking interface should be converted to Special Cycle transactions on the host interface. Secondary PCI Bus Number Register Default = 00h
PCICFG 19h -
Indicates the number of the PCI bus to which the docking interface of the 82C814 chip is connected. Defaults to 0. The logic uses this value to determine whether Type 1 configuration transactions on the host interface should be converted to Type 0 transactions on the docking interface. Subordinate Bus Number Register Default = 00h
PCICFG 1Ah -
Indicates the number of the highest-numbered PCI bus on the docking interface side. The 82C814 logic uses this value in conjunction with the Secondary Bus Number to determine when to respond to Type 1 configuration transactions on the host interface and pass them onto the docking interface. Defaults to 0. Latency Timer Register Indicates the time-out value for the docking interface. Default = 00h
PCICFG 1Bh
PCICFG 1Ch -
Memory Window 0 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Memory Window 0 Base Address Bits: The 32-bit Memory Window 0 Base Address Register selects the start address of one of two possible CardBus memory windows to the slot interface. Bits [11:0] are read-only and are always 0. The memory windows are globally enabled by bit 04h[1] (Command Register). Prefetching is enabled by bit 3Fh[0] (Bridge Control Register) and defaults to "enabled." The Limit address can be set below the Base address to individually disable a window. Memory Window 0 Base Address Register - Byte 1: Address Bits [15:8] Memory Window 0 Base Address Register - Byte 2: Address Bits [23:16] Memory Window 0 Base Address Register - Byte 3: Address Bits [31:24] Memory Window 0 Limit Address Register - Byte 0: Address Bits [7:0 Default = F0h Default = FFh Default = FFh Default = 00h
PCICFG 1Dh PCICFG 1Eh PCICFG 1Fh PCICFG 20h -
Memory Window 0 Limit Address Bits: The 32-bit Memory Window 0 Limit Address Register selects the end address of Memory Window 0. Bits [11:0] are read-only and are always 0. The minimum window size is always 4KB. Memory Window 0 Limit Address Register - Byte 1: Address Bits [15:8] Memory Window 0 Limit Address Register - Byte 2: Address Bits [23:16] Default = 00h Default = 00h
PCICFG 21h PCICFG 22h
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Table 5-1
7 PCICFG 23h PCICFG 24h -
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 00h Default = 00h
Memory Window 0 Limit Address Register - Byte 3: Address Bits [31:24] Memory Window 1 Base Address Register - Byte 0: Address Bits [7:0]
Memory Window 1 Base Address Bits: The 32-bit Memory Window 1 Base Address Register selects the start address of one of two possible CardBus memory windows to the slot interface. Bits [11:0] are read-only and are always 0. The memory windows are globally enabled by bit 04h[1] (Command Register). Prefetching is enabled by bit 3Fh[1] (Bridge Control Register) and defaults to "enabled." The Limit address can be set below the Base address to individually disable a window. Memory Window 1 Base Address Register - Byte 1: Address Bits [15:8] Memory Window 1 Base Address Register - Byte 2: Address Bits [23:16] Memory Window 1 Base Address Register - Byte 3: Address Bits [31:24] Memory Window 1 Limit Address Register - Byte 0: Address Bits [7:0] Default = F0h Default = FFh Default = FFh Default = 00h
PCICFG 25h PCICFG 26h PCICFG 27h PCICFG 28h -
Memory Window 1 Limit Address Bits: The 32-bit Memory Window 1 Limit Address Register selects the end address of Memory Window 1. Bits [11:0] are read-only and are always 0. The minimum window size is always 4KB. Memory Window 1 Limit Address Register - Byte 1: Address Bits [15:8] Memory Window 1 Limit Address Register - Byte 2: Address Bits [23:16] Memory Window 1 Limit Address Register - Byte 3: Address Bits [31:24] I/O Window 0 Base Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0. Default = 00h Default = 00h Default = 00h Default = 00h Decoding: 0 = 16-bit (AD[31:16] = 0) 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h RO: Always returns 0. Default = 00h Default = 00h Default = 00h
PCICFG 29h PCICFG 2Ah PCICFG 2Bh PCICFG 2Ch
I/O Window 0 Base Address Bits: The 32-bit I/O Window 0 Base Address Register selects the start address of one of two possible CardBus I/O windows to the slot interface. The I/O windows are globally enabled by bit 04h[0] (Command Register). I/O Window 0 Base Address Register - Byte 1: Address Bits [15:8] I/O Window 0 Base Address Register - Byte 2: Address Bits [23:16] I/O Window 0 Base Address Register - Byte 3: Address Bits [31:24] I/O Window 0 Limit Address Register - Byte 0: Address Bits [7:0]
PCICFG 2Dh PCICFG 2Eh PCICFG 2Fh PCICFG 30h I/O Window 0 Limit Address Bits: -
The 32-bit I/O Window 0 Limit Address Register selects the end address of I/O Window 0. The minimum window size is always 4 bytes. I/O Window 0 Limit Address Register - Byte 1: Address Bits [15:8] I/O Window 0 Limit Address Register - Byte 2: Address Bits [23:16] I/O Window 0 Limit Address Register - Byte 3: Address Bits [31:24]
PCICFG 31h PCICFG 32h PCICFG 33h
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Table 5-1
7 PCICFG 34h I/O Window 1 Base Address Bits: The 32-bit I/O Window 1 Base Address Register selects the start address of one of two possible CardBus I/O windows to the slot interface. The I/O windows are globally enabled by bit 04h[0] (Command Register). I/O Window 1 Base Address Register - Byte 1: Address Bits [15:8] I/O Window 1 Base Address Register - Byte 2: Address Bits [23:16] I/O Window 1 Base Address Register - Byte 3: Address Bits [31:24] I/O Window 1 Limit Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0. Default = 00h Default = 00h Default = 00h Default = 00h
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 00h RO: Always returns 0. Decoding: 0 = 16-bit (AD[31:16] = 0) 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h
I/O Window 1 Base Address Register - Byte 0: Address Bits [7:0]
PCICFG 35h PCICFG 36h PCICFG 37h PCICFG 38h I/O Window 1 Limit Address Bits: -
The 32-bit I/O Window 1 Limit Address Register selects the end address of I/O Window 1. The minimum window size is always 4 bytes. I/O Window 1 Limit Address Register - Byte 1: Address Bits [15:8] I/O Window 1 Limit Address Register - Byte 2: Address Bits [23:16] I/O Window 1 Limit Address Register - Byte 3: Address Bits [31:24] Interrupt Line Register for Status Change
PCICFG 39h PCICFG 3Ah PCICFG 3Bh PCICFG 3Ch -
This register is readable and writable per the PCI specification. The logic does not use the value written to this register. Interrupt Pin Register for Status Change Default = 01h
PCICFG 3Dh RO: -
This register reflects the value written to PCICFG 4Ch. It defaults to 01h, selecting PCIRQ0# for the status change (docking station attach/detach) interrupt. If PCICFG 4Ch is written to select an ISA interrupt or no interrupt, this register returns 00h. Bridge Control Register - Byte 0 Force CRST# cycling on slot interface: 1 = Assert CRST# (Default) Response to master abort on slot interface: 1 = Signal with target abort or SERR# Reserved: Write as read. Pass VGA addresses A0000-BFFFFh, 3B0-3BBh, 3C0-3DFh: 0 = No 1 = Yes Bridge Control Register - Byte 1 Reserved. Write as read. Write posting: 0 = Disable 1 = Enable Memory Window 1 prefetch: 0 = Disable 1 = Enable (Default) Reserved Forwarding of SERR# from slot interface to primary PCI bus: 0 = Disable 1 = Enable Default = 03h Memory Window 0 prefetch: 0 = Disable 1 = Enable (Default) Default = 40h Response to parity errors on slot interface: 0 = Ignore 1 = Enable
PCICFG 3Eh Reserved
0 = CRST# high 0 = Ignore
PCICFG 3Fh
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Table 5-1
7 PCICFG 40h Subsystem Vendor Bits: The chipset normally responds to reads of this read-only register with 00h. If the option is selected, the EXTCLK pin can be used as DRVVENID# to enable external logic to drive this data onto the bus. In this case, the chipset claims the access but does not drive any data. Subsystem Vendor Register - Byte 1: Bits [15:8] Subsystem ID Register - Byte 0: Bits [7:0]: Default = 00h Default = 00h
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 00h
Subsystem Vendor Register - Byte 0: Bits [7:0]
PCICFG 41h PCICFG 42h Subsystem ID -
The chipset normally responds to reads of this read-only register with 00h. If the option is selected, the EXTCLK pin can be used as DRVVENID# to enable external logic to drive this data onto the bus. In this case, the chipset claims the access but does not drive any data. Subsystem ID Register - Byte 1: Bits [15:8] Reserved Docking INTA# Interrupt Assignment Register Reserved Default = 00h Default = 00h Default = 01h
PCICFG 43h PCICFG 44h - 47h PCICFG 48h
Docking INTA# Interrupt Assignment (PCIRQ0# Default) - Interrupts from the docking INTA# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode interrupt) is selected, this IRQ must be programmed to Level mode on the host chipset. Level Mode: (FireStar only) 00000 = Disabled 00010 = PCIRQ1# 00001 = PCIRQ0# (Default) 00011 = PCIRQ2# Edge Mode: (Viper-N+ or FireStar) 10000 = IRQ0 10110 = IRQ6 10001 = IRQ1 10111 = IRQ7 10010 = IRQ2 11000 = IRQ8 10011 = IRQ3 11001 = IRQ9 10100 = IRQ4 11010 = IRQ10 10101 = IRQ5 00100 = PCIRQ3# 00101-01111 = Rsrvd 11011 = IRQ11 11100 = IRQ12 11101 = IRQ13 11110 = IRQ14 11111 = IRQ15
PCICFG 49h Reserved
Docking INTB# Interrupt Assignment Register
Default = 02h
Docking INTB# Interrupt Assignment (PCIRQ1# Default) - Interrupts from the docking INTB# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode interrupt) is selected, this IRQ must be programmed to Level mode on the host chipset. Level Mode: (FireStar only) 00000 = Disabled 00010 = PCIRQ1# (Default) 00001 = PCIRQ0# 00011 = PCIRQ2# Edge Mode: (Viper-N+ or FireStar) 10000 = IRQ0 10110 = IRQ6 10001 = IRQ1 10111 = IRQ7 10010 = IRQ2 11000 = IRQ8 10011 = IRQ3 11001 = IRQ9 10100 = IRQ4 11010 = IRQ10 10101 = IRQ5 00100 = PCIRQ3# 00101-01111 = Rsrvd 11011 = IRQ11 11100 = IRQ12 11101 = IRQ13 11110 = IRQ14 11111 = IRQ15
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Table 5-1
7 PCICFG 4Ah Reserved
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 03h
Docking INTC# Interrupt Assignment Register
Docking INTC# Interrupt Assignment (PCIRQ2# Default) - Interrupts from the docking INTC# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode interrupt) is selected, this IRQ must be programmed to Level mode on the host chipset. Level Mode: (FireStar only) 00000 = Disabled 00010 = PCIRQ1# 00001 = PCIRQ0# 00011 = PCIRQ2# (Default) Edge Mode: (Viper-N+ or FireStar) 10000 = IRQ0 10110 = IRQ6 10001 = IRQ1 10111 = IRQ7 10010 = IRQ2 11000 = IRQ8 10011 = IRQ3 11001 = IRQ9 10100 = IRQ4 11010 = IRQ10 10101 = IRQ5 00100 = PCIRQ3# 00101-01111 = Rsrvd 11011 = IRQ11 11100 = IRQ12 11101 = IRQ13 11110 = IRQ14 11111 = IRQ15
PCICFG 4Bh Reserved
Docking INTD# Interrupt Assignment Register Docking INTD# Interrupt Assignment (PCIRQ3# default)
Default = 04h
Docking INTD# Interrupt Assignment (PCIRQ3# Default) - Interrupts from the docking INTD# pin are mapped to this interrupt. Note that if an IRQ (an edge-mode interrupt) is selected, this IRQ must be programmed to Level mode on the host chipset. Level Mode: (FireStar only) 00000 = Disabled 00010 = PCIRQ1# 00001 = PCIRQ0# 00011 = PCIRQ2# Edge Mode: (Viper-N+ or FireStar) 10000 = IRQ0 10110 = IRQ6 10001 = IRQ1 10111 = IRQ7 10010 = IRQ2 11000 = IRQ8 10011 = IRQ3 11001 = IRQ9 10100 = IRQ4 11010 = IRQ10 10101 = IRQ5 PCICFG 4Ch Host controller type: 0 = FireStar (burst two data phases) 1 = Viper-N+ (send single data phase on IRQ driveback) Reserved Docking Detect Interrupt Assignment Register 00100 = PCIRQ3# (Default) 00101-01111 = Rsrvd 11011 = IRQ11 11100 = IRQ12 11101 = IRQ13 11110 = IRQ14 11111 = IRQ15
Default = 01h
Docking Detect Interrupt Assignment - If attachment of a docking station is detected, or if the device attached could not be determined, this interrupt will be generated. This same interrupt will be generated when the docking station is removed. Level Mode: 00000 = Disabled 00001 = PCIRQ0# (Default) 00010 = PCIRQ1# 00011 = PCIRQ2# Edge Mode: 10000 = IRQ0 10001 = IRQ1 10010 = IRQ2 10011 = IRQ3 10100 = IRQ4 10101 = IRQ5 Reserved 00100 = PCIRQ3# 00101 = ACPI0 00110 = ACPI1 00111 = ACPI2 01000 = ACPI3 01001-01111 = Rsrvd
10110 = IRQ6 10111 = IRQ7 11000 = IRQ8 11001 = IRQ9 11010 = IRQ10
11011 = IRQ11 11100 = IRQ12 11101 = IRQ13 11110 = IRQ14 11111 = IRQ15
PCICFG 4Dh
Default = 00h
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Table 5-1
7 PCICFG 4Eh Compaq SIRQ HALT mode request: 0 = Active 1 = Halt Compaq SIRQ QUIET mode request: 0 = Continuous 1 = Quiet Reserved
Base Register Group - PCICFG 00h-4Fh (cont.)
6 5 4 3 2 1 0 Default = 00h Reserved Compaq SIRQ (Compaq Serial IRQ scheme): 0 = Disable 1 = Enable
Serial IRQ Control Register 1 Compaq SIRQ data frame slots. Change only when the Serial IRQ logic is disabled or in Halt state. 0 = 17 slots 1 = 21 slots Compaq SIRQ Start frame width in PCI clocks. Change this setting only when Serial IRQ is disabled or in Halt state. 00 = 4 PCI clocks 01 = 6 PCI clocks 10 = 8 PCI clocks 11 = Reserved
PCICFG 4Fh Compaq SIRQ in HALT state (RO)? 0 = No 1 = Yes Compaq SIRQ in QUIET state (RO)? 0 = No 1 = Yes
Serial IRQ Control Register 2 Reserved
Default = 00h Intel SIRQ (Intel Serial IRQ scheme): 0 = Disable 1 = Enable
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5.3 82C814-Specific Register Group
dock has been detected using CD1-2# and VS1-2. Once the card has been inserted and detected, and the interface automatically set appropriately, software can still override the automatic settings by reading and then writing PCICFG 51h[2:0] as desired. The 82C814 defines many special functions that require enabling and monitoring through a dedicated register set. The 82C814-specific registers at PCICFG 50h-5Fh remain set to their programmed values even after a device is removed from the slot. Also, PCICFG 50h is common to both slot interfaces (i.e. changing the bit in one PCI register set changes it in the other). The following subsections discuss some of the special functions located in the 82C814-Specific Register Group and Table 5-2 gives the register's bit formats.
5.3.4
Dual ISA Buses
5.3.1
IRQLATCH
For the purposes of generating IRQs to the host for chipsets without IRQ driveback handling capability, the 82C814 chip provides IRQLATCH. When this feature is enabled, IRQLAT goes active on a driveback cycle to generate IRQ15-0. In this way, an external latch can be used to directly drive the IRQ lines.
Dual ISA buses are possible with the 82C814 chip used in conjunction with the 82C825 PCI-ISA Bridge chip. This feature depends on the ISA Windows feature of the 82C814 chip, which allows cycles destined for the remote docking ISA bus to be claimed with positive decoding from the primary PCI bus and then retried. If the cycle turns out not to be destined for the docking ISA bus, the 82C814 chip ignores the next retry so that the cycle will be claimed using subtractive decode by the host chipset. The FireStar chip provides an additional feature that allows positive decode of cycles to known local ISA devices. This feature would conflict with the positive decode used by the 82C814 chip. Therefore, the 82C814 chip has the option of decoding on the slow clock instead of on the medium clock. This feature is enabled by writing PCICFG 5Eh[7] = 1. When the feature is selected, the 82C814 logic will monitor the DEVSEL# line to determine whether FireStar (or anyone else) has claimed the cycle by fast or medium decode. Only if DEVSEL# remains high through the medium decode clock will the 82C814 chip claim the cycle. The slow decode feature works only for windows enabled as ISA windows. Other windows will continue to use a medium decode.
5.3.2
CLKRUN#
PCICFG 50h[2] selects whether the CLKRUN# signal to the host will toggle. Normally it will be set for automatic operation. In this mode, the 82C814 logic asserts CLKRUN# only when it wants bus ownership for master cycles, or when it has an interrupt it must send to the host. At all other times, it leaves CLKRUN# tristated and depends on the current PCI bus master to assert CLKRUN# and keep the clock running.
5.3.3
Slot Buffer Enable, Slew Rate, and Threshold Control
PCICFG 51h[2:0] are automatically updated by the card insertion state machine according to whether a 5.0V or 3.3V
Table 5-2
7 PCICFG 50h
Specific Register Group - PCICFG 50h-5Fh
6 5 4 3 2 1 0 Default = 01h CLKRUN# on host interface): 0 = Enabled per PCI 1 = Disabled, CLKRUN# tristated Default = 00h Output Drive Select: 00 = Reserved 01 = Reserved 10 = 3.3V PCI dock 11 = 5.0V PCI dock Reserved Reserved Always = 1
PCI Host Feature Control Register Vendor ID feature selected: 0 = No 1 = Yes IRQLATCH function 0 = Disable (default) 1 = Enable Docking detect debounce: 0 = 0.25 sec 1 = 1.0 sec
Reserved
PCICFG 51h Dock Interface clock divisor: 00 = 1 (Default) 01 = 2 10 = 3 11 = 4 Dock Interfaceclock source: 0 = PCICLK 1 = EXTCLK
Docking Feature Control Register 1 Mode select: 0 = Automatic 1 = Force async Reserved Dock Interface threshold voltage: 0 = 3.3V 1 = 5.0V
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Table 5-2
7 PCICFG 52h Secondary PCICLK Skew: This value selects the approximate delay, in nanoseconds, that the internal secondary PCICLK must be skewed in order to compensate for external buffer delays. 0000 = No delay ..... 1101 = 13ns 0001 = 1ns 1110 = 14ns 0010 = 2ns 1111 = 15ns
Specific Register Group - PCICFG 50h-5Fh (cont.)
6 5 4 3 2 1 0 Default = 0Fh Reserved Type 1 to Type 0 conversion blocked from secondary to primary: 0 = No 1 = Yes (Default) Reserved Register IRQ Driveback Address Register - Byte 0: Address Bits [7:0] Default = 00h Default = 30h
Docking Feature Control Register 2
PCICFG 53h PCICFG 54h -
IRQ Driveback Protocol Address Bits: When the 82C824 logic must generate an interrupt from any source, it follows the IRQ Driveback Protocol and toggles the REQ# line to the host. Once it has the bus, it writes the changed IRQ information to the 32-bit I/O address specified in this register. The host interrupt controller claims this cycle and latches the new IRQ values. Bits 2:0 are reserved to be 000 and are read-only. This register defaults to a value of 33333330h. IRQ Driveback Address Register - Byte 1: Address Bits [15:8] IRQ Driveback Address Register - Byte 2: Address Bits [23:16] IRQ Driveback Address Register - Byte 3: Address Bits [31:24] DRQ Remap Base Address Register - Byte 0: Address Bits [7:0] Default = 33h Default = 33h Default = 33h Default = 00h
-
PCICFG 55h PCICFG 56h PCICFG 57h PCICFG 58h DRQ Remap Base Address Bits: -
-
The distributed DMA protocol requires DMA controller registers for each DMA channel to be individually mapped into I/O space outside the range claimed by ISA devices. Bits A[31:0] of this register specify that base; bits 7:0 are reserved (write 0) because the base address can fall only on 256 byte boundaries. The 82C824 logic uses this base address two ways: 1) to claim accesses to a PCMCIA DMA controller channel; 2) to forward accesses across the bridge to remote devices specified in the DMA Channel Selector Register. DRQ Remap Base Address Register - Byte 1: Address Bits [15:8] DRQ Remap Base Address Register - Byte 2: Address Bits [23:16] DRQ Remap Base Address Register - Byte 3: Address Bits [31:24] DMA Channel Selector Register Channel 6 (DMAC2): Channel 5 (DMAC2): DMAC responsibility (RO): Channel 3 (DMAC1): 1 = On slot interface Channel 2 (DMAC1): 1 = On slot interface Channel 1 (DMAC1): 1 = On slot interface Default = 00h Default = 00h Default = 00h Default = 00h Channel 0 (DMAC1): 1 = On slot interface Default = 00h Window 1 generated SMI: 0 = No 1 = Yes Window 0 generated SMI: 0 = No 1 = Yes
PCICFG 59h PCICFG 5Ah PCICFG 5Bh PCICFG 5Ch Channel 7 (DMAC2): 1 = On slot interface
0 = Not claimed 0 = Not claimed 0 = Not claimed 0 = Secondary (always) 1 = On slot 1 = On slot interface interface 1 = Master
0 = Not claimed 0 = Not claimed 0 = Not claimed 0 = Not claimed
PCICFG 5Dh Window 7 generated SMI: 0 = No 1 = Yes Window 6 generated SMI: 0 = No 1 = Yes
SMI Status Register (Write 1 to clear bit) Window 5 generated SMI: 0 = No 1 = Yes Window 4 generated SMI 0 = No 1 = Yes Window 3 generated SMI: 0 = No 1 = Yes Window 2 generated SMI: 0 = No 1 = Yes
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Table 5-2
7 PCICFG 5Eh Slow decode for ISA windows: 0 = Disable 1 = Enable Prefetch on upstream transactions: 0 = Disable 1 = Enable Posted writes on upstream transactions: 0 = Disable 1 = Enable
Specific Register Group - PCICFG 50h-5Fh (cont.)
6 5 4 3 2 1 0 Default = 07h Retry Limit: These bits relate to the number of times that the 82C814, as a slave, will retry accesses on the primary. If this limit is exceeded, the 82C814 generates SERR# to the host. 000=28 001=210 010=2
12
Primary Retry Limit Register Core voltage: 0 = 3.3V 1 = 5.0V Retry count readback control: 0 = Write posting retries on secondary 1 = Retries on primary
100=216 101=220 110=224 111= Infinite retries (Default) Default = 00h
011=214
PCICFG 5Fh -
82C814 Retry Count Readback Register (RO)
This register returns the number of retry attempts made. More than 256 retries are indicated by FFh. Used for diagnostic purposes. Read-only. Separate counts are maintained for primary and secondary. Bit 5Eh[3] selects the count being read back.
Write-Only: This register is also writable, for factory diagnostic purposes only. Reserved Prototype test mode: 0 = Disable 1 = Enable Force FIFO clear Retry test times: 0 = Normal 1 = Quick Power-up and detect timer: 0 = Normal 1 = Quick
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5.4 CardBus Register Group
nals properly and select the correct voltage for the application. The CardBus-style control and status register group is accessible through two different means. It is always accessible as part of the PCI configuration space at the indexes shown in Table 5-4. In addition, when the CardBus register base address at PCICFG 14h is written to any value other than zero, these same registers can be accessed through the system memory space selected (see Table 5-3). Note that when accessing these registers in PCI memory space, they start from an offset of 00h, not 60h, from the register base address programmed.
Table 5-3
CardBus Register Set in System Memory
Name Socket Event Register Socket Mask Register Socket Present State Register Force Event Register Control Register Reserved
CardBus Base Address plus: 000h 004h 008h 00Ch 010h 014-7FFh
5.4.1
Power Control
PCICFG 70h[6:4] set the external VCC5 and VCC3 pin levels. Because only these two pins are available on the 82C814 interface, the system must be designed to interpret these sig-
Table 5-4
7
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh
6 5 4 3 2 1 0 Default = 00h CCD2# status change: 0 = No 1 = Yes Write 1 to clear CCD1# status change: 0 = No 1 = Yes Write 1 to clear Default = 00h Reserved:
PCICFG 60h / MEMOFST 00h Reserved: Write as read.
Socket Event Register - Byte 0 Power cycle complete: 0 = No 1 = Yes Write 1 to clear
PCICFG 61h / MEMOFST 01h
Socket Event Register - Byte 1 Reserved: Write as read.
PCICFG 62h / MEMOFST 02h
Socket Event Register - Byte 2 Reserved: Write as read.
Default = 00h
PCICFG 63h / MEMOFST 03h
Socket Event Register - Byte 3 Reserved. Write as read.
Default = 00h
PCICFG 64h / MEMOFST 04h Reserved: Write as read.
Socket Mask Register - Byte 0 Power cycle status change event: 0 = Mask 1 = Enable CCD2# status change event: 0 = Mask 1 = Enable CCD1# status change event: 0 = Mask 1 = Enable
Default = 00h Reserved
PCICFG 65h / MEMOFST 05h
Socket Mask Register - Byte 1 Reserved: Write as read.
Default = 00h
PCICFG 66h / MEMOFST 06h
Socket Mask Register - Byte 2 Reserved: Write as read.
Default = 00h
PCICFG 67h / MEMOFST 07h
Socket Mask Register - Byte 3 Reserved: Write as read.
Default = 00h
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Table 5-4
7
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh
6 5 4 3 2 1 0 Default = 00h CCD2-1# state: 00 = Dock attached 01 = No dock attached 10 = No dock attached 11 = No dock attached Default = 00h 5.0V dock detected: 0 = No 1 = Yes Bad VCC Data lost (dock request (outside detached CVS1-2, before transacCCD1-2# tion completed): range): 0 = No 0 = No 1 = Maybe 1 = Yes Default = 00h Reserved
PCICFG 68h / MEMOFST 08h Dock recognized - updated only on card insertion: 0 = Yes 1 = No PCICFG 69h / MEMOFST 09h Reserved: Write as read. Reserved: Write as read.
Socket Present State Register (RO) - Byte 0 Device type - updated only on card insertion: 11 = Docking station All other combinations reserved Power cycle status: 0 = Not successful 1 = Successful Socket Present State Register - Byte 1 Reserved 3.3V dock detected: 0 = No 1 = Yes
PCICFG 6Ah / MEMOFST 0Ah
Socket Present State Register - Byte 2 Reserved: Write as read.
PCICFG 6Bh / MEMOFST 0Bh Socket can sup- Socket can supply Voltage Y: ply Voltage X: 0 = No 1 = Yes 0 = No 1 = Yes
Socket Present State Register - Byte 3 (bits are writeable) Socket can supply 3.3V: 0 = No 1 = Yes Socket can supply 5.0V: 0 = No 1 = Yes Force Event Register - Byte 0 Force device type: 11 = Docking station All other combinations reserved Force power cycle event: 0 = No 1 = Yes Force CCD2# event: 0 = No 1 = Yes Force CCD1# event: 0 = No 1 = Yes Reserved: Write as read.
Default = 30h
PCICFG 6Ch / MEMOFST 0Ch Force dock recognized bit to 1: 0 = No 1 = Yes PCICFG 6Dh / MEMOFST 0Dh Reserved: Write as read. Force retest of CVS1-2, CCD1-2# pins (or force bits): 0 = No 1 = Yes PCICFG 6Eh / MEMOFST 0Eh Reserved: Write as read.
Default = 00h Reserved
Force Event Register - Byte 1 Reserved Force 3.3V dock detected bit to 1: 0 = No 1 = Yes Force Event Register - Byte 2 Reserved: Write as read. Force 5.0V dock detected bit to 1: 0 = No 1 = Yes Force bad VCC request bit to 1: 0 = No 1 = Yes
Default = 00h Force data lost bit to 1: 0 = No 1 = Yes
Default = 00h
PCICFG 6Fh / MEMOFST 0Fh
Force Event Register - Byte 3 Reserved: Write as read.
Default = 00h
PCICFG 70h / MEMOFST 10h Reserved: Write as read. Dock VCC power request: 000 = Power off 001 = Reserved 010 = 5.0V 011 = 3.3V
Control Register - Byte 0 Reserved: Write as read. Reserved 100 = Voltage X 101 = Voltage Y 11x = Reserved
Default = 00h
PCICFG 71h / MEMOFST 11h
Control Register - Byte 1 Reserved: Write as read.
Default = 00h
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Table 5-4
7
CardBus Register Group - PCICFG 60h-74h / MEMOFST 00h-7Fh
6 5 4 3 2 1 0 Default = 00h
PCICFG 72h / MEMOFST 12h
Control Register - Byte 2 Reserved: Write as read.
PCICFG 73h / MEMOFST 13h
Control Register - Byte 3 Reserved: Write as read.
Default = 00h
PCICFG 74h / MEMOFST 14h
Reserved
Default = 00h
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5.5 Docking Station Window Selection Group
that is identical to that of the CardBus windows. However, once the docking station window registers are changed from default state, the CardBus windows are no longer compatible with the CardBus standard register set requirements. For example, if specialized software changes docking station window 4 from its default "memory" setting to make it an I/O window, the next time Card Services accesses that window it will be unable to change it back to a memory window and the application will fail. Once the dock is pulled out and reinserted, the default settings will again be in place and software will be able to use the CardBus register set normally. The remainder of the 82C814 PCI-to-CardBus configuration registers are used to select the memory or I/O address ranges that will be claimed by the bridge and passed onto the secondary PCI bus. These windows overlap in function with the predefined CardBus I/O and memory windows, but are more versatile so as to be used for docking station support. However, applications can use the docking station window selection group to access CardBus cards as well. Windows 4-7 are overlapped with the CardBus memory and I/O windows. Table 5-5 summarizes the features.
5.5.1
Warning on Using Docking Station Windows
5.5.2
Docking Station Window Registers
The docking station access windows allow far more flexibility in cycle selection, masking, etc. than do the CardBus window registers. Whenever the 82C814 chip is reset or the CCD1-2# lines go high (signalling card or docking station removal), the docking station window registers are reset to a default state
The docking station registers are listed in Table 5-5 and Table 5-6 lists the power-on reset default values for the window registers. Table 5-7 follows and includes the default settings for each register.
Table 5-5
Docking Station Access Windows
Default Mask 000FFFh 000FFFh 000003h 000003h 000FFFh 000FFFh 000003h 000003h CardBus Window Name, Bits Decoded None, Decode A[31:12] None, Decode A[31:12] None, Decode A[15:0] None, Decode A[15:0] Memory Window 0, A[31:12] Memory Window 1, A[31:12] I/O Window 0, A[31:2] I/O Window 1, A[31:2] Memory or I/O Selectable? Memory Memory I/O I/O Yes - Defaults to Memory Yes - Defaults to Memory Yes - Defaults to I/O Yes - Defaults to I/O Can Generate SMI#? Yes Yes Yes Yes Yes Yes Yes Yes
Docking Station Access Window # 0 1 2 3 4 5 6 7
Table 5-6
Register/0ffset
Power-on Reset, Card Removal Defaults for Docking Station Window Registers
Window 0 FFFFF000h 00h 0FFFh 00h Window 1 FFFFF000h 00h 0FFFh 00h Window 2 FFFFF000h 00h 03h 00h Window 3 FFFFF000h 00h 03h 00h Window 4 FFFFF000h 00h 0FFFh 68h Window 5 FFFFF000h 00h 0FFFh 68h Window 6 FFFFF000h 00h 03h 00h Window 7 FFFFF000h 00h 03h 00h
Start Address/x0h Stop Address/x4h Decoding Mask/x8h Control /xBh
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5.5.2.1 Cycle Decoding Each window can select either memory or I/O decoding, and allows for a decode range anywhere from one dword to the entire address space. On Windows 4-7, upper address bits from A31 on down can be masked in the comparison, allowing any desired degree of aliasing. 5.5.2.2 Cycle Trapping Instead of passing a claimed cycle onto the intended slave PCI interface, the cycle controller can generate a STOP# or CSTOP# on the master PCI interface (primary PCI interface or slot interface) and cause the controlling device to back off. At the same time, the cycle controller generates an IRQ driveback cycle with SMI# active, therefore converting the cycle into a System Management Interrupt trap. At this point, the master will most likely retry the cycle, at which time the 82C814 will allow it to proceed. It may or may not be able to deliver valid data. The host chipset can then run its SMM code. The SMM code can read the SMI Status Register from the 82C814 to determine the window access that caused the SMI. Once the value has been read, the host must write a 1 back to each SMI indicator bit to re-enable trapping and SMI generation on that window. 5.5.2.3 ISA Window Selection All docking station windows contain the ISA Window Selection bit. When set to 1, the window operation is modified as follows. * When a cycle initiated on the primary is claimed through this window, the cycle will be immediately and automatically retried. * On the docking station side, the 82C825 chip will claim the cycle and wait for positive decode on the ISA bus. - If positive decode is determined, the 82C825 logic will terminate the cycle normally. - If no positive decode can be achieved, the 82C825 logic will terminate the cycle with a Target Abort. Once this occurs, the 82C814 chip will simply ignore the next retry attempt on its primary and allow the cycle to pass to the local ISA bus of the host controller. The retries occur up to the limit defined in PCICFG 5Eh[2:0].
Table 5-7
7 PCICFG 80h
Docking Station Window Registers - PCICFG 80h-FFh
6 5 4 3 2 1 0 Default = 00h
Window 0 Start Address Register - Byte 0: Address Bits [7:0]
Window 0 Start Address Bits: Register bits [31:0] indicate the start address for memory window 0. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 0 Start Address Register - Byte 1: Address Bits [15:8] Window 0 Start Address Register - Byte 2: Address Bits [23:16] Window 0 Start Address Register - Byte 3: Address Bits [31:24] Window 0 Stop Address Register - Byte 0: Address Bits [7:0] Default = F0h Default = FFh Default = FFh Default = 00h
PCICFG 81h PCICFG 82h PCICFG 83h PCICFG 84h Window 0 Stop Address Bits: -
Register bits [31:0] indicate the stop address for memory window 0. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 0 Stop Address Register - Byte 1: Address Bits [15:8] Window 0 Stop Address Register - Byte 2: Address bits [23:16] Window 0 Stop Address Register - Byte 3: Address Bits [31:24] Window 0 Mask Register - Byte 0: Mask Bits [7:0] Default = 00h Default = 00h Default = 00h Default = FFh
PCICFG 85h PCICFG 86h PCICFG 87h PCICFG 88h Window 0 Mask Bits: -
Mask register bits [23:12] allow Window 0 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [11:0] are always 1 (masked). Mask register bits [23:0] are fixed to 000FFFh to force a 4KB boundary
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Table 5-7
7 PCICFG 89h PCICFG 8Ah PCICFG 8Bh Window points to ISA bus: 0 = No 1 = Yes Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window PCICFG 8Ch-8Fh PCICFG 90h Window 1 Start Address Bits: Register bits [31:0] indicate the start address for memory window 1. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 1 Start Address Register - Byte 1: Address Bits [15:8] Window 1 Start Address Register - Byte 2: Address Bits [23:16] Window 1 Start Address Register - Byte 3: Address Bits [31:24] Window 1 Stop Address Register - Byte 0: Address Bits [7:0] Default = F0h Default = FFh Default = FFh Default = 00h Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window Reserved Window 1 Start Address Register - Byte 0: Address Bits [7:0] Default = 00h Default = 00h
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 3 2 1 0 Default = 0Fh Default = 00h Default = 08h Window 0 Trap/SMI#: 0 = Disable 1 = Enable Reserved
Window 0 Mask Register - Byte 1: Mask Bits [15:8] Window 0 Mask Register - Byte 2: Mask Bits [23:16] Window 0 Control Register Reserved Cycle qualifier: 0 = I/O 1 = Memory (always)
PCICFG 91h PCICFG 92h PCICFG 93h PCICFG 94h Window 1 Stop Address Bits: -
Register bits [31:0] indicate the stop address for memory window 0. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 1 Stop Address Register - Byte 1: Address Bits [15:8] Window 1 Stop Address Register - Byte 2: Address bits [23:16] Window 1 Stop Address Register - Byte 3: Address Bits [31:24] Window 1 Mask Register - Byte 0: Mask Bits [7:0] Default = 00h Default = 00h Default = 00h Default = FFh
PCICFG 95h PCICFG 96h PCICFG 97h PCICFG 98h Window 1 Mask Bits: -
Mask register bits [23:12] allow Window 0 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [11:0] are always 1 (masked). Mask register bits [23:0] are fixed to 000FFFh to force a 4KB boundary Window 1 Mask Register - Byte 1: Mask Bits [15:8] Window 1 Mask Register - Byte 2: Mask Bits [23:16] Window 1 Control Register Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window Reserved Cycle qualifier: 0 = I/O 1 = Memory (always) Window 1 Trap/SMI#: 0 = Disable 1 = Enable Default = 0Fh Default = 00h Default = 08h Reserved
PCICFG 99h PCICFG 9Ah PCICFG 9Bh Window points to ISA bus: 0 = No 1 = Yes
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Table 5-7
7 PCICFG 9Ch-9Fh PCICFG A0h Window 2 Start Address Bits: Register bits [31:0] indicate the start address for I/O window 2. Bits [31:16] are read only and always return 0.
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 Reserved Window 2 Start Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0 3 2 1 0 Default = 00h Default = FCh Decoding: 0 = 16-bit (always) AD[31:16] = 0 1 = 32-bit Default = FFh Default = 00h Default = 00h Default = 00h
PCICFG A1h PCICFG A2h PCICFG A3h PCICFG A4h Window 2 Stop Address Bits: -
Window 2 Start Address Register - Byte 1: Address Bits [15:8] Window 2 Start Address Register - Byte 2: Address Bits [23:16] Window 2 Start Address Register - Byte 3: Address Bits [31:24] Window 2 Stop Address Register - Byte 0: Address Bits [7:0]
Register bits [31:0] indicate the stop address for I/O window 2. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 2 Stop Address Register - Byte 1: Address Bits [15:8] Window 2 Stop Address Register - Byte 2: Address Bits [23:16] Window 2 Stop Address Register - Byte 3: Address Bits [31:24] Window 2 Mask Register - Byte 0: Mask Bits [7:0] Default = 00h Default = 00h Default = 00h Default = 03h
PCICFG A5h PCICFG A6h PCICFG A7h PCICFG A8h Window 2 Mask Bits: -
Mask register bits [23:0] are fixed to 000003h to force a four-byte granularity. Window 2 Mask Register - Byte 1: Mask Bits [15:8] Window 2 Mask Register - Byte 2: Mask Bits [23:16] Window 2 Control Register Reserved Reserved Reserved Cycle qualifier: 0 = I/O (always) 1 = Memory Window 2 Trap/SMI#: 0 = Disable 1 = Enable Default = 00h Default = FCh RO: Always returns 0 Decoding: 0 = 16-bit (always) AD[31:16] = 0 1 = 32-bit Default = FFh Default = 00h Default = 00h Default = 00h Default = 00h Default = 00h Reserved
PCICFG A9h PCICFG AAh PCICFG ABh Window points to ISA bus: 0 = No 1 = Yes PCICFG ACh-AFh PCICFG B0h Window 3 Start Address Bits: -
Reserved Window 3 Start Address Register - Byte 0: Address Bits [7:0]
Register bits [31:0] indicate the start address for I/O window 3. Bits [31:16] are read only and always return 0 to indicate a minimum 4KB boundary.
PCICFG B1h PCICFG B2h PCICFG B3h
Window 3 Start Address Register - Byte 1: Address Bits [15:8] Window 3 Start Address Register - Byte 2: Address Bits [23:16] Window 3 Start Address Register - Byte 3: Address Bits [31:24]
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Table 5-7
7 PCICFG B4h Window 3 Stop Address Bits: Register bits [31:0] indicate the stop address for I/O window 3. Bits [11:0] are read only and always return 0 to indicate a minimum 4KB boundary. Window 3 Stop Address Register - Byte 1: Address Bits [15:8] Window 3 Stop Address Register - Byte 2: Address Bits [23:16] Window 3 Stop Address Register - Byte 3: Address Bits [31:24] Window 3 Mask Register - Byte 0: Mask Bits [7:0] Default = 00h Default = 00h Default = 00h Default = 00h
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 3 2 1 0 Default = 00h
Window 3 Stop Address Register - Byte 0: Address Bits [7:0]
PCICFG B5h PCICFG B6h PCICFG B7h PCICFG B8h Window 3 Mask Bits: -
Mask register bits [23:0] are fixed to 000003h to force a four-byte granularity. Window 3 Mask Register - Byte 1: Mask Bits [15:8] Window 3 Mask Register - Byte 2: Mask Bits [23:16] Window 3 Control Register Reserved Reserved Reserved Cycle qualifier: 0 = I/O (always) 1 = Memory Reserved Window 4 Start Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0 Window 3 Trap/SMI#: 0 = Disable 1 = Enable Default = 00h Default = 00h If memory: reads 0. If I/O: Decoding 0 = 16-bit AD[31:16] = 0 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h RO: Always returns 0 Default = 00h Default = 00h Default = 00h Default = 00h Default = 00h Default = 00h Reserved
PCICFG B9h PCICFG BAh PCICFG BBh Window points to ISA bus: 0 = No 1 = Yes PCICFG BCh-BFh PCICFG C0h Window Start Address Bits: -
Register bits [31:0] indicate the start address for one of the eight memory or I/O windows. The selection between memory or I/O, as well as other feature selections, are made through the Window 4 Control Register.
PCICFG C1h PCICFG C2h PCICFG C3h PCICFG C4h -
Window 4 Start Address Register - Byte 1: Address Bits [15:8] Window 4 Start Address Register - Byte 2: Address Bits [23:16] Window 4 Start Address Register - Byte 3: Address Bits [31:24] Window 4 Stop Address Register - Byte 0: Address Bits [7:0] Window 4 Address Bits:
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows. Window 4 Stop Address Register - Byte 1: Address Bits [15:8] Window 4 Stop Address Register - Byte 2: Address Bits [23:16] Window 4 Stop Address Register - Byte 3: Address Bits [31:24]
PCICFG C5h PCICFG C6h PCICFG C7h
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Table 5-7
7 PCICFG C8h Window 4 Mask Bits: Mask register bits [23:2] allow Window 4 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [1:0] are always 11 (masked). Window 4 Mask Register - Byte 1: Mask Bits [15:8] Window 4 Mask Register - Byte 2: Mask Bits [23:16] Window 4 Control Register Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window PCICFG CCh-CFh PCICFG D0h Window 5 Start Address Bits: Register bits [31:0] indicate the start address for one of the eight memory or I/O windows. The selection between memory or I/O, as well as other feature selections, are made through the Window 5 Control Register. Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window Reserved Window 5 Start Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0 Default = 00h Default = 00h If memory: reads 0. If I/O: Decoding 0 = 16-bit AD[31:16] = 0 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h RO: Always returns 0 Default = 00h Default = 00h Default = 00h Default = 00h RO: Always returns 1. Reserved Cycle qualifier: 0 = I/O 1 = Memory (Default) Window 4 Trap/SMI#: 0 = Disable 1 = Enable
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 3 2 1 0 Default = 00h RO: Always returns 1.
Window 4 Mask Register - Byte 0: Mask Bits [7:0]
PCICFG C9h PCICFG CAh PCICFG CBh Window points to ISA bus: 0 = No 1 = Yes
Default = 00h Default = 00h Default = 48h Reserved
PCICFG D1h PCICFG D2h PCICFG D3h PCICFG D4h Window 5 Stop Address Bits: -
Window 5 Start Address Register - Byte 1: Address Bits [15:8] Window 5 Start Address Register - Byte 2: Address Bits [23:16] Window 5 Start Address Register - Byte 3: Address Bits [31:24] Window 5 Stop Address Register - Byte 0: Address Bits [7:0]
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows. Window 5 Stop Address Register - Byte 1: Address Bits [15:8] Window 5 Stop Address Register - Byte 2: Address Bits [23:16] Window 5 Stop Address Register - Byte 3: Address Bits [31:24] Window 5 Mask Register - Byte 0: Mask Bits [7:0]
PCICFG D5h PCICFG D6h PCICFG D7h PCICFG D8h Window 5 Mask Bits: -
Mask register bits [23:2] allow Window 4 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [1:0] are always 11 (masked). Window 5 Mask Register - Byte 1: Mask Bits [15:8] Window 5 Mask Register - Byte 2: Mask Bits [23:16]
PCICFG D9h PCICFG DAh
Default = 00h Default = 00h
OPTi
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Table 5-7
7 PCICFG DBh Window points to ISA bus: 0 = No 1 = Yes Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window PCICFG DCh-DFh PCICFG E0h Window 6 Address Bits: Register bits [31:0] indicate the start address for one of the eight memory or I/O windows. The selection between memory or I/O, as well as other feature selections, are made through the Window 6 Control Register. Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 3 2 1 0 Default = 48h Window 5 Trap/SMI#: 0 = Disable 1 = Enable Reserved
Window 5 Control Register Reserved Cycle qualifier: 0 = I/O 1 = Memory (Default)
Reserved Window 6 Start Address Register - Byte 0: Address Bits [7:0] RO: Always returns 0
Default = 00h Default = 00h If memory: reads 0. If I/O: Decoding 0 = 16-bit AD[31:16] = 0 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h RO: Always returns 0 Default = 00h Default = 00h Default = 00h Default = 03h RO: Always returns 1.
PCICFG E1h PCICFG E2h PCICFG E3h PCICFG E4h Window 6 Stop Address Bits: -
Window 6 Start Address Register - Byte 1: Address Bits [15:8] Window 6 Start Address Register - Byte 2: Address Bits [23:16] Window 6 Start Address Register - Byte 3: Address Bits [31:24] Window 6 Stop Address Register - Byte 0: Address Bits [7:0]
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows. Window 6 Stop Address Register - Byte 1: Address Bits [15:8] Window 6 Stop Address Register - Byte 2: Address Bits [23:16] Window 6 Stop Address Register - Byte 3: Address bits [31:24] Window 6 Mask Register - Byte 0: Mask Bits [7:0]
PCICFG E5h PCICFG E6h PCICFG E7h PCICFG E8h Window 6 Mask Bits: -
Mask register bits [23:2] allow Window 4 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [1:0] are always 11 (masked). Window 6 Mask Register - Byte 1: Mask Bits [15:8] Window 6 Mask Register - Byte 2: Mask Bits [23:16] Window 6 Control Register Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window Reserved Reserved Cycle qualifier: 0 = I/O (Default) 1 = Memory Window 6 Trap/SMI#: 0 = Disable 1 = Enable
PCICFG E9h PCICFG EAh PCICFG EBh Window points to ISA bus: 0 = No 1 = Yes
Default = 00h Default = 00h Default = 00h Reserved
PCICFG ECh-EFh
Default = 00h
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Table 5-7
7 PCICFG F0h Window 7 Address Bits: Register bits [31:0] indicate the start address for one of the eight memory or I/O windows. The selection between memory or I/O, as well as other feature selections, are made through the Window 7 Control Register.
Docking Station Window Registers - PCICFG 80h-FFh (cont.)
6 5 4 3 2 1 0 Default = 00h RO: Always returns 0 If memory: reads 0. If I/O: Decoding 0 = 16-bit AD[31:16] = 0 1 = 32-bit Default = F0h Default = FFh Default = FFh Default = 00h RO: Always returns 0 Default = 00h Default = 00h Default = 00h Default = 03h RO: Always returns 1. Window 7 Stop Address Register - Byte 1: Address Bits [15:8] Window 7 Stop Address Register - Byte 2: Address Bits [23:16] Window 7 Stop Address Register - Byte 3: Address Bits [31:24] Window 7 Mask Register - Byte 0: Mask Bits [7:0]
Window 7 Start Address Register - Byte 0: Address Bits [7:0]
PCICFG F1h PCICFG F2h PCICFG F3h PCICFG F4h Window 7 Stop Address Bits: -
Window 7 Start Address Register - Byte 1: Address Bits [15:8] Window 7 Start Address Register - Byte 2: Address Bits [23:16] Window 7 Start Address Register - Byte 3: Address Bits [31:24] Window 7 Stop Address Register - Byte 0: Address Bits [7:0]
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
PCICFG F5h PCICFG F6h PCICFG F7h PCICFG F8h Window 7 Mask Bits: -
Mask register bits [23:2] allow Window 4 to be aliased throughout the memory or I/O address space. Setting any bit to a 1 masks out the comparison on this bit. The register should be written to 0 to decode the entire address. Bits [1:0] are always 11 (masked). Window 7 Mask Register - Byte 1: Mask Bits [15:8] Window 7 Mask Register - Byte 2: Mask Bits [23:16] Window 7 Control Register Reads are prefetchable: 0 = No 1 = Yes Set to 0 for I/O window Writes can be posted: 0 = No 1 = Yes Set to 0 for I/O window Reserved Reserved Cycle qualifier: 0 = I/O (Default) 1 = Memory Window 7 Trap/SMI#: 0 = Disable 1 = Enable
PCICFG F9h PCICFG FAh PCICFG FBh Window points to ISA bus: 0 = No 1 = Yes
Default = 00h Default = 00h Default = 00h Reserved
PCICFG FCh-FFh
Default = 00h
OPTi
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5.6 Register Summary
and Status Register Group can also be accessed in system memory space. Refer to Section 5.4 for details regarding accessing those memory locations. Table 5-8 summarizes the locations, register names, and default values for register set of the 82C814. Note that the table lists only the PCICFG location, the CardBus Control
Table 5-8
Loc.
82C814 Register Summary
Default Loc. 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h Register Name Memory Window 0 Limit Address Register Byte 0: Address Bits [7:0 Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Memory Window 1 Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Memory Window 1 Limit Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] I/O Window 0 Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] I/O Window 0 Limit Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] I/O Window 1 Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] I/O Window 1 Limit Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Interrupt Line Register for Status Change Interrupt Pin Register for Status Change Bridge Control Register Byte 0 Byte 1 Subsystem Vendor Register Byte 0: Bits [7:0] Byte 1: Bits [15:8] Subsystem ID Register Byte 0: Bits [7:0]: Byte 1: Bits [15:8] Default 00h 00h 00h 00h 00h F0h FFh FFh 00h 00h 00h 00h 00h F0h FFh FFh 00h 00h 00h 00h 00h F0h FFh FFh 00h 00h 00h 00h 00h 01h 40h 03h 00h 00h 00h 00h
Register Name
PCICFG 00h-4Fh: Base Register Group 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Vendor Identification Register (RO) Byte 0 Byte 1 Device ID (RO) Byte 0 Byte 1 PCI Command Register Byte 0 Byte 1 PCI Status Register Byte 0 Byte 1 Revision Register (RO) Prgrm Interface Class Code Register (RO) Class Code Register (RO) Byte 0 Byte 1 Cache Line Size Register Latency Timer Register Header Type Register BIST Register CardBus Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Reserved PCI Secondary Bus Status Register Byte 0 Byte 1 Primary PCI Bus Number Register Secondary PCI Bus Number Register Subordinate Bus Number Register Latency Timer Register Memory Window 0 Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] 45h 10h 14h C8h 04h 00h 00h 02h 00h 00h 07h 06h 00h 00h 02h 00h 00h 00h 00h 00h 00h
00h 02h 00h 00h 00h 00h 00h F0h FFh FFh
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Table 5-8 82C814 Register Summary (cont.)
Loc. 44h47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh Register Name Reserved Docking INTA# Interrupt Assignment Register Docking INTB# Interrupt Assignment Register Docking INTC# Interrupt Assignment Register Docking INTD# Interrupt Assignment Register Docking Detect Interrupt Assignment Register Reserved Serial IRQ Control Register 1 Serial IRQ Control Register 2 Default 00h 01h 02h 03h 04h 01h 00h 00h 00h 70h 71h 72h 73h 74h 6Ch 6Dh 6Eh 6Fh Loc. Register Name Force Event Register Byte 0 Byte 1 Byte 2 Byte 3 Control Register Byte 0 Byte 1 Byte 2 Byte 3 Reserved Default 00h 00h 00h 00h 00h 00h 00h 00h 00h
PCICFG 80h-FFh: Docking Station Window Registers 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch9Fh Window 0 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 0 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address bits [23:16] Byte 3: Address Bits [31:24] Window 0 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 0 Control Register Reserved Window 1 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 1 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address bits [23:16] Byte 3: Address Bits [31:24] Window 1 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 1 Control Register Reserved 00h F0h FFh FFh 00h 00h 00h 00h FFh 0Fh 00h 08h 00h
PCICFG 50h-5Fh: Specific Register Group 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh PCI Host Feature Control Register Docking Feature Control Register 1 Docking Feature Control Register 2 Reserved IRQ Driveback Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] DRQ Remap Base Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] DMA Channel Selector Register SMI Status Register (Write 1 to clear bit) Primary Retry Limit Register 82C814 Retry Count Readback Register (RO) 01h 00h 0Fh 00h 30h 33h 33h 33h 00h 00h 00h 00h 00h 00h 07h 00h
00h F0h FFh FFh 00h 00h 00h 00h FFh 0Fh 00h 08h 00h
PCICFG 60h-74h: CardBus Register Group 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh Socket Event Register Byte 0 Byte 1 Byte 2 Byte 3 Socket Mask Register Byte 0 Byte 1 Byte 2 Byte 3 Socket Present State Register Byte 0 (RO) Byte 1 Byte 2 Byte 3 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 30h
OPTi
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Table 5-8 82C814 Register Summary (cont.)
Loc. A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh AChAFh B0h B1h B2h B3h Register Name Window 2 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 2 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 2 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 2 Control Register Reserved Window 3 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 3 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 3 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 3 Control Register Reserved Window 4 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 4 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 4 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 4 Control Register Reserved Default FCh FFh 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h FCh FFh 00h 00h Loc. D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DChDFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh EChEFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FChFFh Register Name Window 5 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 5 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 5 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 5 Control Register Reserved Window 6 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 6 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address bits [31:24] Window 6 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 6 Control Register Reserved Window 7 Start Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 7 Stop Address Register Byte 0: Address Bits [7:0] Byte 1: Address Bits [15:8] Byte 2: Address Bits [23:16] Byte 3: Address Bits [31:24] Window 7 Mask Register Byte 0: Mask Bits [7:0] Byte 1: Mask Bits [15:8] Byte 2: Mask Bits [23:16] Window 7 Control Register Reserved Default 00h F0h FFh FFh 00h 00h 00h 00h 00h 00h 00h 48h 00h
00h F0h FFh FFh 00h 00h 00h 00h 03h 00h 00h 00h 00h
B4h B5h B6h B7h B8h B9h BAh BBh BChBFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CChCFh
00h 00h 00h 00h 00h 00h 00h 00h 00h
00h F0h FFh FFh 00h 00h 00h 00h 00h 00h 00h 48h 00h
00h F0h FFh FFh 00h 00h 00h 00h 03h 00h 00h 00h 00
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6.0 Electrical Ratings
other conditions above those indicated in the operational sections of this specification are not implied. Stresses above those listed in the following tables may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any
6.1
Absolute Maximum Ratings
5.0 Volt 3.3 Volt Max +6.5 -0.5 -0.5 0 -40 VCC + 0.5 VCC + 0.5 +70 +125 -0.5 -0.5 0 -40 Min Max +4.0 VCC + 0.5 VCC + 0.5 +70 +125 Unit V V V C C
Symbol VCC VI VO TOP TSTG
Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature
Min
6.2
VIL VIH VOL VOH IIL IOZ CIN COUT ICC
DC Characteristics: VCC = 3.3V or 5.0V 5%, TA = 0C to +70C
Parameter Input low Voltage Input high Voltage Output low Voltage Output high Voltage Input Leakage Current Tristate Leakage Current Input Capacitance Output Capacitance Power Supply Current 3.3V Core 5.0V Core +2.4 +10.0 +10.0 +10.0 +10.0 90 120 Min -0.5 +2.0 Max +0.8 VCC + 0.5 +0.4 Unit V V V V A A pF pF mA Fully active IOL = 4.0mA IOH = -1.6mA VIN = VCC Condition
Symbol
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6.3
Sym
AC Characteristics
Parameter Min Max Unit Figure
Primary PCI Bus t100 t101 t102 t103 t104 t105 C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# setup time to PCICLK rising C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# hold time from PCICLK rising C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# valid delay from PCICLK rising REQ# setup time to PCICLK rising REQ# hold time from PCICLK rising GNT# valid delay from PCICLK rising 7 0 2 12 0 2 12 11 ns ns ns ns ns ns 6-1 6-2 6-3 6-1 6-2 6-3
Secondary PCI Bus t200 t201 t202 t203 t204 t205 t206 t207 t208 CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#, CBLOCK#, CPAR, CSERR#, CPERR# setup time to PCICLK rising CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#, CBLOCK#, CPAR, CSERR#, CPERR# hold time from PCICLK rising CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#, CBLOCK#, CPAR, CSERR#, CPERR# valid delay from PCICLK rising CREQ[3:0]# setup time to PCICLK rising CREQ[3:0]# hold time from PCICLK rising CGNT[3:0]# valid delay from PCICLK rising PCIRQ[3:0]# setup time to PCICLK rising PCIRQ[3:0]# hold time from PCICLK rising PCIRQ[3:0]# valid delay from PCICLK rising 7 0 2 12 0 2 5 3 2 16 12 11 ns ns ns ns ns ns ns ns ns 6-1 6-2 6-3 6-1 6-2 6-3 6-1 6-2 6-3
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6.4 AC Timing Diagrams
Setup Timing Waveform
0ns 50ns 100ns
Figure 6-1
PCICLK
t100, t103, t200, t203, t206 SIGNAL
Figure 6-2
Hold Timing Waveform
0ns
50ns
100ns
PCICLK t101, t104, t201, t204, t207
SIGNAL
Figure 6-3
Output Delay Timing Waveform
0ns
50ns
100ns
PCICLK
t102, t105, t202, t203, t205, t208 SIGNAL
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7.0 Mechnical Package Outline
144-Pin TQFP, Thin Quad Flat Pack
Figure 7-1
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IRQ Driveback
Appendix A IRQ Driveback Protocol
The OPTi PCI IRQ Driveback cycle provides a clean and simple way to convey interrupt and DMA status information to the host. The protocol is reliable and does not in any way compromise PCI compatibility. 1. Whenever a PCI peripheral device must signal an IRQ or SMI# to the system, it asserts its REQ# line to the host for one PCI clock, deasserts it for one PCI clock, then asserts it again and keeps it low until acknowledged. The host recognizes this sequence as a high-priority request and immediately removes all other bus grants (GNT# lines). Once the previous bus owner is off the bus, the host acknowledges the high-priority request with GNT# as usual. The peripheral device logic runs an I/O write cycle to the IRQ Driveback address specified in the PCI configuration registers, and releases REQ#. The host latches the information on AD[31:0] and sets the IRQ lines appropriately. An optional second burst data cycle can take place to convey additional interrupt information. cycle request is illustrated in the figure. A second data phase is also possible.
A.1
Driveback Cycle Format
2.
The charts below illustrate the interrupt information indicated IRQ bits indicate whether that IRQ line is being driven high or low. The EN# bits indicate whether that IRQ is enabled to be changed or not. When the EN# bit is low, the value on the IRQ bit is valid. The device containing the central interrupt controller claims this I/O write cycle, and can then change its internal IRQ line state to match the value sent. When a PCI device needs to generate an interrupt to the system, it runs a driveback cycle with the Enable bit low for each IRQ line under its control. For example, a device on PCI could run a driveback cycle with IRQ3 high and EN3# low to generate IRQ3 to the system. When the interrupt has been serviced and the device deasserts its interrupt, it starts another driveback cycle with IRQ3 low and EN3# low. During both of these instances, if the device controls interrupts other than IRQ3, it must set its EN# bits low for all channels it controls, not just for the interrupt whose state has changed. The other IRQs must be driven with their previously used values.
3.
4. 5.
PCI-type devices on the secondary side of bridge chips can use this same protocol to convey their interrupt requests through the bridge to the host. The format of the driveback
Figure A-1
IRQ Driveback Cycle High-Priority Request
PCICLK REQ# GNT#
// // // //
AD[31:0]
Table A-1
Low Word High Word AD15
Information Provided on a Driveback Cycle
AD14 AD13 AD12 AD11 AD10 AD9 IRQ9 AD25 AD8 IRQ8 AD24 EN8# AD7 IRQ7 AD23 EN7# AD6 IRQ6 AD22 EN6# AD5 IRQ5 AD21 EN5# AD4 IRQ4 AD20 EN4# AD3 IRQ3 AD19 EN3# AD2 IRQ2 AD18 EN2# AD1 IRQ1 AD17 EN1# AD0 IRQ0 AD16 EN0#
IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 AD31 AD30 AD29 AD28 AD27 AD26
EN15# EN14# EN13# EN12# EN11# EN10# EN9#
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IRQ Driveback
There is a convention for assignment of otherwise unusable IRQs: * IRQ2 generates an SMI#. Note that the sense of IRQ2 is still active high. In this way, devices that use IRQ driveback can generate SMI# simply by routing their normal interrupt to IRQ2 without needing to change the polarity of the interrupt generation logic. * IRQ13 generates an NMI. This feature allows PCI-to-ISA bridges such as the 82C825 chip to return the CHCK# signal from the ISA bus across the PCI bus. The sense of IRQ13 is active high. Table A-2 illustrates the format of the optional second data phase of the IRQ driveback cycle. This phase is presently reserved for returning the PCI interrupts and ACPI Events. If the device needs to send back level-model interrupts, it bursts the information on the PCI clock following data phase one. The IRQ driveback address automatically increments to (base +4) per PCI requirements. It is also allowable for devices to drive back only phase 2, by directly accessing the (base +4) address.
Table A-2
Low Word AD15 Rsvd
Information Provided on a Optional Data Phase 2 of IRQ Driveback Cycle
AD14 Rsvd AD13 Rsvd AD12 Rsvd AD11 Rsvd AD10 Rsvd AD9 Rsvd AD8 Rsvd AD7 ACPI3 AD6 ACPI2 AD5 ACPI1 AD4 ACPI0 AD3 AD2 AD1 PCIRQ 1 AD0 PCIRQ 0
PCIRQ PCIRQ 3 2
High Word
AD31 Rsvd
AD30 Rsvd
AD29 Rsvd
AD28 Rsvd
AD27 Rsvd
AD26 Rsvd
AD25 Rsvd
AD24 Rsvd
AD23
AD22
AD21
AD20
AD19
AD18 ENP2#
AD17 ENP1#
AD16 ENP0#
EN EN EN EN ENP3# ACPI3# ACPI2# ACPI1# ACPI0#
A.2
Edge vs Level Mode, IRQ Polarity
The IRQs driven back in data phase 1 are interpreted as edge-mode interrupts, as expected for AT compatibility. The AD[15:0] signals are interpreted as active when high (1); the Enable (EN#) signals AD[31:16] are active when low (0). In optional data phase 2, the PCIRQ0-3 bits are interpreted as level-mode interrupts by the host hardware. As with data phase 1, the controls indicated by AD[15:0] are interpreted as active when high; the Enable (EN#) controls on AD[31:16] are active when low. Note that PCI signals INTA-D# are active low by definition.
However, the INTA-D# lines can be shared by multiple devices on the PCI bus. Thus, one device could perform an IRQ driveback to set the INTx# line active for its purposes, while another device could follow immediately by setting the same INTx# line inactive. Therefore, the host is required to implement a counter in this case, so that it considers the line inactive only after it has received the same number of activegoing drivebacks as it has inactive-going drivebacks. A three-bit counter can be considered sufficient to handle the situation, since this would allow up to seven devices to chain to the same interrupt. It is unlikely that system requirements would exceed this number given the latency penalty incurred.
A.3
Host Handling of IRQ Driveback Information
The host chipset must handle the IRQ driveback information differently depending on whether the selected interrupt is sharable or not. Generally the ISA IRQ lines need no special consideration.
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A.4 External Implementation Figure A-2
AD12 AD28 AD11 AD27 AD10 AD26 AD9 AD25 IRQLATCH
Dynamic Resourcing
IRQ12 EN12# IRQ11 EN11#
An IRQ driveback-capable device can implement the signal IRQLATCH. IRQLATCH allows IRQs to be driven onto the ISA bus directly through external TTL. There are two possible support circuits. Static Resourcing - Using a single 74373 latch provides direct control of up to eight IRQ lines. However, the selected IRQs are always under the control of the IRQ driveback device, even if the device is not actively using the IRQs. They cannot be dynamically reassigned to other devices. Figure A3 shows a typical connection. Dynamic Resourcing - Uses one 74373 latch and one 74125 tristate buffer to provide dynamic control over four specific IRQ lines; each four line group requires an additional 74373/74125 pair. Dynamic control allows the interrupt to be driven only when it has been assigned to a sub-function of the IRQ driveback device; otherwise, the output remains tristated and is open for use by other system devices. The figure below shows a typical connection. Note that if the IRQLATCH function is selected on the primary, devices on the secondary are no longer free to generate any IRQ. They are limited to the IRQs supported through the latch.
74373
EN10#
IRQ10 IRQ9 EN9#
Figure A-3
Static Resourcing
IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ5 IRQ4 IRQ3
AD12 AD11 A10 AD9 AD7 AD5 AD4 AD3 IRQLATCH
74373
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Sales Information
HEADQUARTERS:
OPTi Inc. 888 Tasman Drive Milpitas, CA 95035 tel: 408-486-8000 fax: 408-486-8011
Florida
Engineered Solutions Ind., Inc. 1000 E. Atlantic Blvd., Ste. #202 Pompano Beach, FL 33060 tel: 305-784-0078 fax: 305-781-7722
Lyons Corp. 4615 W. Streetsboro Richfield, OH 44286 tel: 216-659-9224 fax: 216-659-9227 Lyons Corp. 248 N. State St. Westerville, OH 43081 tel: 614-895-1447 fax: Same
India
Spectra Innovation Unit S-822 Manipal Centre 47 Dickenson Road Bangalore 560-042 Kamataka, India tel: 91-80-558-8323/3977 fax: 91-80-558-6872
SALES OFFICES:
Japan
OPTi Japan KK Murata Building 6F, 2-22-7 Ohhashi Meguro-ku Tokyo 153, Japan tel: 81-3-5454-0178 fax: 81-3-5454-0168
Georgia
Concord Component Reps 6825 Jimmy Carter Blvd., Ste. #1303 Norcross, GA 30071 tel: 770-416-9597 fax: 770-441-0790
Israel
Ralco Components (1994) Ltd. 11 Benyamini St. 67443 Tel Aviv Israel tel: 972-3-6954126 fax: 972-3-6951743
Texas
Axxis Technology Marketing, Inc. 701 Brazos, Suite 500 Austin, TX 78701 tel: 512-320-9130 fax: 512-320-5730 Axxis Technology Marketing, Inc. 6804 Ashmont Drive Plano, TX 75023 tel: 214-491-3577 fax: 214-491-2508
Illinois
Micro-Tex, Inc. 1870 North Roselle Rd., Ste. #107 Schaumburg, IL 60195-3100 tel: 708-885-8200 fax: 708-885-8210
Taiwan
OPTi Inc. 9F, No 303, Sec 4, Hsin Yih Road Taipei, Taiwan, ROC tel: 886-2-325-8520 fax: 886-2-325-6520
Korea
Woo Young Tech Co., Ltd. 5th Floor Koami Bldg 13-31 Yoido-Dong Youngduengpo-Ku Seoul, Korea 150-010 tel: 02-369-7099 fax: 02-369-7091
Massachusetts
S-J Associates, Inc. 40 Mall Road, Suite 202 Burlington, MA 01803 tel: 617-272-5552 fax: 617-272-5515
United Kingdom & Europe
OPTi Inc. Bicester Business Center Market Court, Victoria Road Bicester, Oxon OX6 7QB U.K. tel: + 44-1-869-321-622 fax: + 44-1-869-241-448
Virginia
S-J Associates, Inc. 900 S. Washington St., Ste. #307 Falls Church, VA 22046 tel: 703-533-2233 fax: 703-533-2236
Singapore
Instep Microsolutions Pte Ltd. 629 Aljunied Road #05-15 Cititech Industrial Building Singapore 1438 tel: 65-741-7507 65-741-7530 fax: 65-741-1478
Michigan
Jay Marketing 44752 Helm Street., Ste. A Plymouth, MI 48170 tel: 313-459-1200 fax: 313-459-1697
Wisconsin
Micro-Tex, Inc. 22660 Broadway, Ste. #4A Waukesha, WI 53186 tel: 414-542-5352 fax: 414-542-7934
United States
OPTi Inc. 8 Corporate Park, Ste. #300 Irvine, CA 92714-5117 tel: 714-838-0589 fax: 714-838-9753 OPTi Inc. 4400 N. Federal Highway, Ste. #120 Boca Raton, FL 33431 tel: 407-395-4555 fax: 407-395-4554 OPTi Inc. 20405 State Highway 249, Ste. #220 Houston, TX 77070 tel: 713-257-1856 fax: 713-257-1825
New Jersey
S-J Associates, Inc. 131-D Gaither Dr. Mt. Laurel, NJ 08054 tel: 609-866-1234 fax: 609-866-8627
South America
Uniao Digital Rua Guido Caloi Bloco B, Piso 3 Sao Paulo-SP, CEP 05802-140 Brazil tel: 55-11-5514-3355 fax: 55-11-5514-1088
International
Australia
Braemac Pty. Ltd. Unit 6, 111 Moore St., Leichhardt Sydney, 2040 Australia tel: 61-2-550-6600 fax: 61-2-550-6377
New York
S-J Associates, Inc. 265 Sunrise Highway Rockville Centre, NY 11570 tel: 516-536-4242 fax: 516-536-9638 S-J Associates, Inc. 735 Victor-Pittsford Victor, NY 14564 tel: 716-924-1720
Switzerland
REPRESENTATIVES: United States
Alabama/Mississippi
Concord Component Reps 190 Line Quarry Rd., Ste. #102 Madison, AL 35758 tel: 205-772-8883 fax: 205-772-8262
North & South Carolina
Concord Component Reps 10608 Dunhill Terrace Raleigh, NC 27615 tel: 919-846-3441 fax: 919-846-3401
Ohio/W. Pennsylvania
Lyons Corp. 4812 Fredrick Rd., Ste. #101 Dayton, OH 45414 tel: 513-278-0714 fax: 513-278-3609
California - Southern
Jones & McGeoy Sales 5100 Campus Dr., Ste. #300 Newport Beach, CA 92660 tel: 714-724-8080 fax: 714-724-8090
Datacomp AG Silbernstrasse 10 8953 Dietikon Switzerland China tel: 41-1-740-5140 Legend Electronic Components. Ltd. fax: 41-1-741-3423 Unit 413, Hong Kong Industrial Technology Centre United Kingdom 72 Tat Chee Avenue Spectrum Kowloon Tong, Hong Kong 2 Grange Mews, tel: 852-2776-7708 Station Road fax: 852-2652-2301 Launton, Bicester Oxfordshire,OX6 0DX France UK Tekelec Airtronic, France tel: 44-1869-325174 5, Rue Carle Vernet fax: 44-1869-325175 92315 Sevres Cedex France MMD tel: 33-1-46-23-24-25 3 Bennet Court, fax: 33-1-45-07-21-91 Bennet Road Reading Germany Berkshire, RG2 0QX UK Kamaka tel: 44 1734 313232 Rheinsrasse 22 fax: 44 1734 313255 76870 Kandel Germany tel: 49-7275-958211 fax: 49-7275-958220
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The information contained within this document is subject to change without notice. OPTi Inc. reserves the right to make changes in this manual at any time as well as in the products it describes, at any time without notice or obligation. OPTi Inc. assumes no responsibility for any errors contained within. In no event will OPTi Inc. be liable for any damages, direct, indirect, incidental or consequential resulting from any error, defect, or omission in this specification. Copyright (c) 1996 by OPTi Inc. All rights reserved. OPTi is a trademark of OPTi Incorporated. All other brand and product names are trademarks or copyrights of their respective owners.
OPTi Inc. * 888 Tasman Drive * Milpitas, CA 95035 * (408) 486-8000
OPTi Inc.
888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 WWW: http://www.opti.com/

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